Timing Violation Detection in Integrated Circuit Registers
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Solution Overview
Problem
Existing methods for improving integrated circuit performance by detecting timing violations require adding detection circuits to each synchronous device, leading to reduced performance and increased cost and silicon area.
Innovation Solution
A method that identifies subsets of synchronous devices with critical input paths and simulations to select devices for detection circuits, coupled to both clock and data inputs, reducing the need for extensive detection circuitry by focusing on critical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If detection circuits are added to each synchronous device to detect timing violations, then timing violation detection capability is improved, but circuit performance deteriorates and silicon area increases
Solution Approach 1:
The patent segments the circuit into critical and non-critical paths through static timing analysis. Detection circuits are selectively applied only to synchronous devices on critical paths (those with slack time below a threshold), rather than uniformly to all synchronous devices. This segmentation maintains timing violation detection capability for critical paths while avoiding the performance penalty of adding detection circuits to non-critical paths.
Solution Approach 2:
The patent applies different quality levels of detection to different parts of the circuit. Critical paths receive full detection coverage with detection circuits added to synchronous devices, while non-critical paths receive no detection coverage. This local quality approach ensures reliable detection where timing violations would most impact performance, while preserving overall circuit performance by avoiding unnecessary detection circuits elsewhere.
2Reliability
If detection circuits are added to each synchronous device to detect timing violations, then timing violation detection capability is improved, but silicon area increases
Solution Approach 1:
The patent segments the circuit based on timing criticality, identifying only critical paths through static timing analysis that require detection. By adding detection circuits only to synchronous devices on critical paths rather than all synchronous devices, the silicon area required for detection is significantly reduced while maintaining adequate timing violation detection capability.
3Reliability
If safety margin is increased to account for PVT variations, then reliability is improved, but circuit performance deteriorates
Solution Approach 1:
The patent performs static timing analysis beforehand to identify critical paths and synchronous devices that are most susceptible to timing violations under PVT variations. By preemptively adding detection circuits only to these identified critical devices, the circuit maintains reliability under PVT variations without needing to over-design all paths with excessive safety margins, thereby preserving performance.
Data Source
AI summary
A method of circuit conception including performing static timing analysis on a circuit design to identify a first subset of the synchronous devices having at least one input path with a slack time below a first threshold; simulating the circuit design using one or more functional test patterns to identify a second subset of the synchronous devices for which the number of activations during the simulation is above a second threshold; selecting at least one synchronous device forming part of both of the first and second subsets; and modifying the circuit design to include, for each selected synchronous device, a detection circuit coupled to one or more inputs of the selected synchronous device.