Timing Violation Detection in Pruned Circuit Data
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Solution Overview
Problem
Current Electronic Design Automation (EDA) systems face inefficiencies in timing signoff verification and correction for integrated circuit designs, characterized by repeated iterations, divergent analyses, long turnaround times, excessive storage and processing requirements, and truncated analyses, leading to costly delays and potential design flaws.
Innovation Solution
A system and method that includes a timing analysis module, a data reduction module, and a correction module to detect and correct timing violations in electronic circuit designs by selectively reducing timing data based on detected violations, optimizing physical implementation, and minimizing recursive loops between signoff and physical implementation modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comprehensive timing analysis is performed on all physical implementation data, then timing violation detection accuracy is improved, but processing time and computational resources increase significantly
Solution Approach 1:
The patent segments the comprehensive timing analysis into two phases: (1) a preliminary phase that identifies only timing violations, and (2) a detailed phase that performs comprehensive analysis only on regions containing violations. This segmentation allows the system to maintain high detection accuracy while significantly reducing overall processing time by avoiding unnecessary analysis of compliant regions.
Solution Approach 2:
The patent applies local quality by performing different levels of analysis on different regions of the physical implementation data. Regions with timing violations receive detailed comprehensive analysis, while regions without violations receive minimal or no analysis. This localized approach concentrates computational resources where they are most needed, improving both accuracy and efficiency.
2Loss of information
If full timing data is retained for all circuit regions, then analysis comprehensiveness is improved, but storage and memory requirements become untenable
Solution Approach 1:
The patent extracts and retains only the timing data corresponding to regions with detected timing violations, discarding or minimizing storage of data from compliant regions. This extraction approach maintains all necessary information for analyzing actual problems while dramatically reducing storage and memory requirements to manageable levels.
Solution Approach 2:
The patent discards timing data from regions that do not contain violations, as this data is not needed for the correction process. The system recovers and retains only the essential timing data from violation regions, achieving both storage efficiency and analysis comprehensiveness for the critical areas.
3Manufacturing precision
If repeated iterations between timing signoff and physical implementation are performed, then timing correction accuracy is improved, but turnaround time becomes inordinate
Solution Approach 1:
The patent performs preliminary identification of timing violations and their affected regions before initiating detailed correction analysis. By pre-identifying the scope and location of violations, the system prepares the necessary timing data in advance, enabling more efficient correction processing and reducing the need for repeated full-cycle iterations between timing signoff and physical implementation.
Data Source
AI summary
A system and method for expeditious operational timing signoff of a circuit design through a timing analysis and subsequent corrective or remedial optimization is performed with the goal of correlating timing between the physical implementation corrective optimizer module and the timing analysis module to reduce iterations therebetween. A physical optimizer in the correction module is imparted with knowledge of the physical implementation of the design to allow for legal, non-conflicting placement of corrective buffers or resizing of gates in accordance with the physical implementation data of the circuit design.