Timing-Violation PUF Circuit Using a Carry Lookahead Adder
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Solution Overview
Problem
Existing software physical unclonable function (SPUF) circuits face issues of high hardware overhead, low efficiency, and reliability due to complex quantization processes and stochastic noise, making them inefficient and unreliable.
Innovation Solution
A timing-violation software physical unclonable function circuit using a combinatorial logic pipeline architecture with a carry lookahead adder as the arithmetic operation cell, generating PUF responses by triggering timing violations without additional hardware, utilizing a 2m-bit input register and (m+1)-bit sampling register to produce unique responses through clock-controlled operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 12-bit TDC is used to quantize the transmission path delay in a 32-bit multiplier, then PUF responses can be obtained, but hardware overhead increases significantly
Solution Approach 1:
The patent extracts only the necessary 2 bits from the TDC output that satisfy PUF response requirements, discarding the remaining 10 bits. This extraction approach reduces hardware overhead by eliminating the need to process and store all 12 bits, while still obtaining valid PUF responses.
Solution Approach 2:
Instead of using a complex 12-bit TDC quantization approach, the patent inverts the approach by directly utilizing timing violation information from the combinatorial logic pipeline. This alternative method achieves PUF functionality without requiring a full 12-bit quantization circuit, thereby reducing hardware overhead.
2Reliability
If a 12-bit TDC is used for quantization, then PUF responses are obtained, but hardware resources are wasted since only 2 bits are actually used
Solution Approach 1:
The patent extracts only the 2 most significant bits from the timing violation detection process that are needed for PUF responses. This selective extraction eliminates the hardware resources required for processing the remaining 10 bits, directly addressing the resource waste problem.
Solution Approach 2:
The patent applies partial action by using only the necessary 2 bits for PUF functionality rather than performing full 12-bit quantization. This partial approach consumes fewer hardware resources while still achieving the required PUF response generation capability.
3Reliability
If the internal transmission path of a 32-bit multiplier is used, then PUF entropy is obtained, but the complex structure requires validity checking which reduces efficiency
Solution Approach 1:
The patent uses the combinatorial logic pipeline's own timing characteristics to generate PUF responses. The pipeline naturally produces timing violations under specific clock conditions, eliminating the need for separate validity checking circuits and improving response generation efficiency.
Solution Approach 2:
The patent performs preliminary validation by designing the combinatorial logic pipeline and register cells to inherently produce valid timing violations under specified clock frequencies. This preliminary design ensures that timing violations occur naturally without requiring post-processing validity checks, thereby improving efficiency.
4Measurement precision
If stochastic noise in the quantization process is present, then actual measurement is achieved, but PUF response reliability decreases
Solution Approach 1:
The patent converts the harmful effect of stochastic noise into a beneficial feature by using timing violations as the entropy source. Timing violations are deterministic under specific clock conditions but exhibit natural variation across different hardware instances, providing both measurement precision and response reliability without being affected by quantization noise.
Data Source
AI summary
A timing-violation software physical unclonable function circuit including combinatorial logic pipeline architecture is provided. The combinatorial logic pipeline architecture serves as a hardware platform. The combinatorial logic pipeline architecture includes an arithmetic operation cell, and the arithmetic operation cell includes a carry lookahead adder for performing add operations. The timing-violation software physical unclonable function circuit generates PUF response outputs by triggering timing violations in the combinatorial logic pipeline architecture.