Timing Window Sliding for Crosstalk Pessimism Reduction
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Solution Overview
Problem
Existing methods for identifying undesirable electrical interactions (capacitive crosstalk) in integrated circuits are pessimistic, leading to false identification of aggressors and timing violations due to the use of variation-aware windows that account for process variations, resulting in unnecessary design changes and increased fabrication costs.
Innovation Solution
A computer-programmed method that adjusts timing windows for victim and aggressor nets by a specific amount to account for variations across a wafer, allowing for more accurate overlap analysis and reducing pessimism in crosstalk analysis by sliding the timing windows of each net instance to align their midpoints, thereby reducing false aggressor identification and timing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If variation-aware timing windows are used to account for process variations, then the analysis covers more process corners, but pessimism increases leading to false aggressor identification
Solution Approach 1:
The patent segments the timing window into two distinct components: a variation-aware component that accounts for process variations across wafer, and a deterministic component that provides precise timing boundaries. This segmentation allows each component to serve its specific function without the other's drawbacks, resolving the contradiction between comprehensive coverage and precise measurement.
Solution Approach 2:
The patent introduces a new dimension to timing window analysis by separating spatial variation (across wafer) from temporal precision (timing boundaries). This dimensional separation enables the timing window to simultaneously capture process variations while maintaining accurate timing measurements, eliminating false aggressor identification.
2Reliability
If conservative timing windows are used to ensure all process corners are covered, then reliability is improved, but timing violation detection becomes overly sensitive
Solution Approach 1:
The timing window is segmented into variation-aware and deterministic portions, where the variation-aware portion provides reliability through process corner coverage while the deterministic portion prevents false timing violation detection by establishing precise boundaries. This resolves the contradiction between reliability and harmful false detections.
Solution Approach 2:
Different portions of the timing window are assigned different qualities: the variation-aware component provides broad coverage for reliability, while the deterministic component provides local precision to avoid false violations. This local differentiation resolves the contradiction between comprehensive coverage and false sensitivity.
3Measurement precision
If timing windows are adjusted to reduce pessimism, then false aggressor identification decreases, but analysis accuracy must be maintained
Solution Approach 1:
The patent segments the timing window adjustment into controlled portions: the variation-aware component is adjusted to reduce pessimism and false positives, while the deterministic component maintains analysis accuracy by preserving precise timing boundaries. This segmentation enables both goals to be achieved simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces pessimism in crosstalk analysis by eliminating unnecessary timing violations and design changes, improving the accuracy of identifying actual aggressors and reducing the complexity of wafer fabrication processes.
Implementation Method 1
remove an amount that changes across a wafer as a function of variation parameter(s), from each net's timing window
Data Source
AI summary
A computer is programmed to identify a number of groups of timing windows, each group including a victim timing window and one (or more) aggressor timing window(s), respectively for a victim net and one (or more) aggressor nets in an IC design. The computer automatically slides (i.e. shifts in time) the victim and aggressor timing windows as a group for each die, i.e. by a specific amount that is identical for all timing windows of an instance of a coupled stage in a die, but differs for other instances of the same coupled stage in other dies. Crosstalk analysis is then performed, using time-shifted timing windows which result from sliding, to identify overlapping victim and aggressor nets, followed by variation aware delay calculations to identify timing violations and timing critical nets, followed by revision of the IC design, which is eventually fabricated in a wafer of semiconductor material.