Timing-Based Yield Calculation for Circuit Design Modification
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Solution Overview
Problem
Existing semiconductor processing variations affect the performance and yield of integrated circuits, and current static timing analysis methods do not adequately address the need for robust circuit design without overdesigning, which can lead to inefficiencies in power and area usage.
Innovation Solution
A timing-based yield calculation is used to modify circuit designs by determining yield probability values, ranking paths based on their contribution to yield probability loss, and applying targeted modifications to improve timing and yield probability while adhering to power and area constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static timing analysis is performed over varying conditions to determine best- and worst-case timing delays, then timing robustness is improved, but power consumption and area increase due to overdesigning
Solution Approach 1:
The patent applies parameter changes by modifying the timing analysis approach from deterministic best-case/worst-case analysis to statistical timing analysis that incorporates process variations as probability distributions. This allows the design to meet timing requirements with a specified yield probability rather than guaranteeing worst-case performance, thereby reducing the need for overdesigning and lowering power consumption
Solution Approach 2:
The patent implements partial action by applying timing adjustments only to the specific percentage of worst-performing paths (e.g., top 10% or 20%) rather than all paths in the circuit. This selective approach improves timing robustness for the critical portion of paths while avoiding the excessive power consumption and area overhead that would result from optimizing all paths
2Reliability
If static timing analysis is performed over varying conditions to determine best- and worst-case timing delays, then timing robustness is improved, but area increases due to overdesigning
Solution Approach 1:
The patent changes the design parameter from deterministic timing margins to statistical timing margins based on yield probability. By specifying a target yield probability (e.g., 95% or 99%), the design can use smaller timing margins for the majority of paths, reducing the area overhead associated with buffer insertion and cell sizing that would be required for worst-case guarantees
Solution Approach 2:
The patent applies area-efficient adjustments only to the critical subset of paths that fall within the specified worst-performing percentage. This selective optimization avoids the excessive area consumption that would result from applying timing adjustments to all paths, thereby improving timing robustness with minimal area penalty
3Reliability
If targeted modifications are applied to improve timing of worst-performing paths, then yield probability is improved, but device complexity increases
Solution Approach 1:
The patent segments the circuit paths into performance-based groups (e.g., worst 10%, middle 80%, best 10%) and applies different timing adjustment strategies to each segment. This segmentation allows yield probability improvement through focused modifications on the critical worst-performing paths while maintaining simplicity for the majority of paths, thereby limiting overall circuit complexity
Data Source
AI summary
Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.