Timing Yield Computation via Correlated Sample Generation

The patent segments the full-chip timing analysis by identifying and isolating yield-critical timing paths from the complete design. Instead of analyzing all timing paths simultaneously, the method extracts only the critical paths that contribute most to timing yield variations, performing Monte Carlo simulations on these segmented paths only. This segmentation reduces the computational burden while maintaining prediction accuracy for timing yield.

The patent extracts yield-critical timing paths from the full chip design by analyzing path sensitivity and correlation characteristics. The method identifies and separates the most influential timing paths that drive yield variations, removing them from the full-chip analysis set. This extraction allows focused computational resources on the critical subset of paths, significantly reducing runtime while preserving timing yield prediction accuracy.

The patent applies local quality by generating correlated samples selectively for timing arcs that are shared by multiple critical paths. Instead of applying correlation modeling uniformly across all timing paths, the method identifies local regions (timing arcs) where correlations are most impactful and applies correlated sample generation only to these specific locations. This localized approach reduces overall computational complexity while maintaining accuracy where it matters most.

The patent uses partial action by performing correlated sample generation only for the subset of timing arcs that are common to multiple critical paths, rather than exhaustively analyzing all timing arcs in the design. This partial application of correlation modeling achieves sufficient accuracy for yield prediction while significantly reducing computational complexity compared to full-chip correlation analysis.