TiN Blocking Structure for Metal Diffusion Prevention
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Solution Overview
Problem
The traditional gate stack configuration in semiconductor devices, particularly with silicon dioxide gate dielectric and poly-silicon gate electrodes, faces challenges in miniaturization, leading to a need for improved gate stack configurations, such as those with metal gate electrodes and high-k gate dielectrics, which require further enhancements to address issues like metal diffusion and electrical performance.
Innovation Solution
A blocking structure comprising multiple layers, including a metal diffusion prevention layer (pTiN) and an electrical performance enhancement layer (mTiN), is introduced to prevent metal diffusion and enhance carrier mobility by applying appropriate stress to the channel region, utilizing TiN layers with varying Ti/N ratios to achieve these effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate electrode and high-k gate dielectric configuration is used to improve electrical performance, then carrier mobility and switching speed are enhanced, but metal diffusion into the gate dielectric occurs causing reliability degradation
Solution Approach 1:
A blocking structure comprising multiple TiN layers is introduced as an intermediary between the metal gate electrode and the gate dielectric. This blocking structure prevents metal diffusion into the gate dielectric while maintaining electrical performance, effectively resolving the contradiction between reliability improvement and metal diffusion prevention.
Solution Approach 2:
The blocking structure uses a composite multi-layer configuration of TiN layers with different Ti/N ratios. The combination of pTiN (Ti/N<1) and mTiN (Ti/N≥1) layers creates a composite material system that simultaneously provides diffusion barrier properties and electrical performance enhancement.
2Object-generated harmful factors
If a blocking structure with multiple TiN layers is introduced to prevent metal diffusion, then metal diffusion is reduced, but device complexity increases
Solution Approach 1:
The TiN layers are formed with different Ti/N ratios (pTiN with Ti/N<1 and mTiN with Ti/N≥1) to achieve different functional properties. By changing the compositional parameter of the TiN material, the blocking structure simultaneously provides diffusion barrier functionality and electrical performance enhancement without requiring entirely separate layers.
Solution Approach 2:
The multi-layer TiN blocking structure serves multiple functions: it acts as a diffusion barrier to prevent metal migration, provides stress control for carrier mobility enhancement, and maintains electrical conductivity. This multi-functionality reduces the need for additional separate layers, thereby limiting the increase in device complexity.
3Reliability
If TiN layers with varying Ti/N ratios are used to enhance carrier mobility through stress, then electrical performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies target Ti/N ratio ranges for different layers (pTiN: Ti/N<1, mTiN: Ti/N≥1) to achieve the desired balance between diffusion prevention and electrical performance. By defining clear parameter ranges rather than single values, the manufacturing precision requirement is made more practical while still achieving the technical effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces metal diffusion and enhances electrical performance by maintaining adequate conductivity and increasing carrier mobility, thereby improving the switching speed and drive current in semiconductor devices.
Implementation Method 1
a first layer, and the first layer comprises a TiN layer has a Ti/N ratio greater than 1... the second layer is configured as a diffusion barrier to a metallic material
Implementation Method 2
an electrical performance enhancement layer over the metal diffusion prevention layer... configured to enhance carrier mobility by applying appropriate stress to the channel region
Data Source
AI summary
A method of manufacturing a semiconductor device, and the method includes forming a stack of a work function layer, a blocking structure, and a metal cap layer sequentially on a substrate. The forming of the blocking structure includes sequentially depositing at least a metal diffusion prevention layer over the work function layer and an electrical performance enhancement layer over the metal diffusion prevention layer before forming the metal cap layer. The electrical performance enhancement layer includes a TiN layer having a Ti/N ratio greater than 1.