TiN High-k CMOS Gates With Dual Workfunction Annealing
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Solution Overview
Problem
Achieving the optimal workfunction for both p-channel and n-channel metal-oxide-semiconductor (PMOS and NMOS) transistors in high dielectric constant (hi-k) dielectric and metal gate transistors is complicated and expensive, particularly in conventional manufacturing processes.
Innovation Solution
A process is developed to form integrated circuits with PMOS TiN metal gates having a workfunction greater than 4.85 eV and NMOS TiN metal gates with a workfunction less than 4.25 eV, utilizing specific deposition and annealing techniques for TiN metal gates and high-k dielectrics, ensuring minimal degradation and flexibility in process flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional processing methods are used to achieve different work functions for NMOS and PMOS transistors, then the desired workfunction values are obtained, but the processing becomes complicated and expensive
Solution Approach 1:
The patent applies local quality by implementing different annealing conditions for NMOS and PMOS regions. Specifically, NMOS regions receive nitrogen annealing to achieve workfunction < 4.3 eV, while PMOS regions receive oxygen annealing to achieve workfunction > 4.8 eV. This localized treatment allows different work functions to be achieved on the same TiN gate material without requiring different gate metals or complex masking steps, thereby reducing processing complexity while maintaining precise workfunction control.
Solution Approach 2:
The patent utilizes parameter changes by varying the annealing atmosphere (nitrogen vs. oxygen) and temperature conditions to control the workfunction of TiN gates. By changing the chemical environment during annealing, the workfunction can be precisely tuned: nitrogen annealing reduces workfunction for NMOS applications, while oxygen annealing increases it for PMOS applications. This approach eliminates the need for different gate metal materials and simplifies the manufacturing process.
2Manufacturing precision
If different gate metals or hi-k gate dielectrics are used for NMOS and PMOS transistors, then the optimal workfunction is achieved, but the manufacturing cost increases
Solution Approach 1:
The patent implements universality by using a single TiN gate metal material for both NMOS and PMOS transistors. The multi-functionality is achieved through post-deposition annealing treatments that can selectively adjust the workfunction of TiN gates depending on the transistor type. This eliminates the need for separate gate metal deposition processes for NMOS and PMOS, reducing manufacturing complexity and cost while maintaining optimal workfunction values for both transistor types.
Solution Approach 2:
The patent applies parameter changes by modifying the annealing conditions (atmosphere composition, temperature, duration) of the TiN gate to achieve different workfunctions. For NMOS transistors, nitrogen-containing atmospheres are used to reduce workfunction below 4.3 eV, while for PMOS transistors, oxygen-containing atmospheres are used to increase workfunction above 4.8 eV. This single-material approach with parameter variation significantly reduces manufacturing cost compared to using different gate metals.
3Device complexity
If hi-k dielectric is deposited first and gate material is stripped and replaced with metal gate, then the process is simpler, but the hi-k dielectric may be exposed to degrading chemicals
Solution Approach 1:
The patent applies preliminary action by forming the TiN gate metal layer before depositing the hi-k dielectric layer. This sequence ensures that the hi-k dielectric is never exposed to chemicals that could degrade it, as the gate metal serves as a protective barrier. The workfunction of the TiN gate is subsequently adjusted through annealing treatments after the hi-k dielectric is in place, achieving the desired workfunction values without compromising dielectric integrity.
Solution Approach 2:
The patent inverts the conventional process sequence by depositing the gate metal (TiN) before the hi-k dielectric, rather than the typical approach of depositing dielectric first and then adding gate material. This inversion protects the hi-k dielectric from degrading chemicals throughout the entire processing sequence, while still allowing for subsequent workfunction adjustment of the TiN gate through controlled annealing in nitrogen or oxygen atmospheres.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves the desired workfunctions for both PMOS and NMOS transistors with reduced complexity and cost, maintaining the integrity of high-k dielectrics and allowing for different dielectrics to be used on each transistor type.
Implementation Method 1
an oxygen anneal of a 10 nm thick TiN layer to obtain a high work function
Implementation Method 2
a nitrogen anneal to obtain a low work function
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
In described examples, an integrated circuit is formed with a thick TiN metal gate (146) with a work function greater than 4.85 eV and with a thin TiN metal gate (156) with a work function less than 4.25 eV. An integrated circuit is formed with a replacement gate PMOS TiN metal gate transistor (170) with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor (172) with a workfunction less than 4.25 eV. An integrated circuit is formed with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.