TiN eFuse Memory Cell Layout for Lower Voltage Scaling
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Solution Overview
Problem
Existing eFuse memory cells require large cell areas and high programming voltages, making them unsuitable for advanced technology nodes due to the limitations of traditional resistor materials and fabrication processes.
Innovation Solution
Implementing a metal-based layer, such as titanium nitride (TiN), as the fuse resistor in the eFuse memory cell, which can be formed during the back-end-of-line (BEOL) or middle-end-of-line (MEOL) process, reducing cell size and programming voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional resistor materials and fabrication processes are used in eFuse memory cells, then the device can be manufactured with existing processes, but the cell area becomes large and programming voltage becomes high
Solution Approach 1:
The patent changes the material parameter from traditional resistor materials to metal-based layers (such as TiN, TaN, or W), which fundamentally alters the electrical and physical properties. This material substitution enables smaller cell area and lower programming voltage while remaining compatible with BEOL/MEOL fabrication processes
Solution Approach 2:
The invention uses composite structures combining metal-based layers with insulating layers to form MIM (metal-insulator-metal) capacitor structures that serve as fuse elements. This composite approach enables the desired electrical characteristics for eFuse operation while achieving reduced cell area
2Device complexity
If traditional resistor materials are used in eFuse memory cells, then the device structure can be maintained, but the programming voltage becomes high
Solution Approach 1:
By changing the resistive element from traditional materials to metal-based layers, the electrical parameters (resistance, breakdown characteristics) are fundamentally improved, enabling lower programming voltage operation while keeping the 1T1R device structure intact
Solution Approach 2:
The patent substitutes traditional semiconductor-based resistors with metal-based layers that have superior electrical properties, replacing a material system with one that inherently provides lower voltage operation without requiring structural complexity increases
3Ease of manufacture
If traditional resistor materials are used, then existing fabrication processes can be utilized, but the eFuse memory cells are not scalable for future technology nodes
Solution Approach 1:
The material substitution to metal-based layers provides parameters (resistivity, breakdown voltage, dimensional control) that scale better with technology node shrinkage, enabling future-proof eFuse designs while using standard BEOL/MEOL processes
Solution Approach 2:
The invention transitions from planar resistor structures to vertically-integrated MIM capacitor structures, utilizing the vertical dimension for the fuse element. This dimensional change enables better scaling as technology nodes shrink, since the critical dimensions are controlled in the vertical stacking direction rather than lateral dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a metal-based layer like TiN as the fuse resistor reduces the cell area and programming voltage, enabling eFuse memory cells to be scalable for future technology nodes while maintaining functionality.
Implementation Method 1
a metal-based layer with a resistivity configured to irreversibly transition from a first resistance state to a second resistance state
Data Source
AI summary
A memory device is disclosed. The memory device includes a transistor. The memory device includes a resistor electrically coupled to the transistor, the transistor and the resistor forming an electrical fuse (eFuse) memory cell. The memory device includes a plurality of interconnect structures formed over a source/drain structure of the transistor. The memory device includes a plurality of via structures formed over the source/drain structure of the transistor. The resistor is disposed between the source/drain structure of the transistor and a topmost one of the plurality of interconnect structures. The resistor is formed of titanium nitride (TiN).