TiN Gate Electrode Oxygen Gradient Silicon Diffusion
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Solution Overview
Problem
In the manufacturing of semiconductor devices with metal-insulator-polysilicon stack (MIPS) elements, there is a challenge in reducing silicon diffusion and preventing an increase in equivalent oxide thickness (EOT) due to the interaction between metal gate electrodes and high dielectric films, which affects the work function and reliability of the transistors.
Innovation Solution
A semiconductor device and manufacturing method involving a gate electrode stack with a conductive layer containing titanium, nitrogen, and oxygen, where the oxygen concentration is highest at the interface with the silicon layer, reducing silicon diffusion and oxygen incorporation into the gate dielectric film, thereby maintaining the work function and suppressing EOT growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a metal gate electrode is used to avoid poly-Si depletion, then the driving current is improved, but silicon diffusion into the metal gate occurs during heat treatment, reducing the work function
Solution Approach 1:
A TiN layer is introduced as an intermediary between the poly-Si gate electrode and the high-k dielectric film. This intermediate layer prevents direct interaction and silicon diffusion between the poly-Si and metal gate, while maintaining the high-k dielectric properties and enabling proper work function control during subsequent heat treatment processes.
Solution Approach 2:
The gate structure employs a composite configuration combining poly-Si, TiN, and high-k dielectric materials. This composite structure leverages the advantages of each material: poly-Si provides mechanical strength and electrical connectivity, TiN offers diffusion barrier properties and work function control, and the high-k dielectric enables thin effective oxide thickness with low leakage current.
2Length of moving object
If the gate dielectric film is made thinner to reduce gate length, then the device size is reduced, but gate leakage current increases
Solution Approach 1:
The patent transitions from conventional SiO2/SiNx gate dielectrics to high-k dielectric materials (such as HfO2, ZrO2, or their silicates/nitrides). This parameter change in dielectric constant allows achieving thinner effective oxide thickness (EOT) for scaled device dimensions while maintaining physically thicker films that suppress gate leakage current through their superior insulating properties.
3Stability of the object's composition
If TiN is formed by CVD at low temperature to achieve high work function, then the work function is improved, but the process temperature control becomes more difficult
Solution Approach 1:
The patent specifies forming TiN by CVD at low temperatures (not more than 450°C) using TiCl4 and NH3 precursors. This parameter change in formation temperature, combined with controlled stoichiometry and phase structure ((100) orientation), enables achieving high work function (not less than 4.8 eV) while maintaining process control and compatibility with existing CMOS fabrication sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces silicon diffusion and oxygen incorporation, maintaining the work function stability and preventing EOT increase, thus enhancing the reliability and performance of the semiconductor devices.
Implementation Method 1
reducing silicon diffusion and oxygen incorporation into the gate dielectric film
Implementation Method 2
oxidizing a surface of the first metal nitride layer by introducing oxygen gas and performing heat treatment
Data Source
AI summary
Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.