TiN Floating Gate Protection in Super Flash Erase Structures
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Solution Overview
Problem
The existing super flash manufacturing methods face issues with the oxidation of the TiN floating gate, leading to high erase voltage and slow erase rate due to the TiN layer being prone to oxidization, especially at the top region, which affects the erase performance.
Innovation Solution
Incorporating a third silicon nitride layer as a protective layer between the second oxide layer and the HTO oxide layer, and a fifth silicon nitride layer to prevent oxidation of the TiN layer during the HTO oxidation process, improving the structural continuity of the TiN floating gate and enhancing erase performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If HTO oxidation process is used to form oxide layers, then oxide layer formation is achieved, but TiN floating gate oxidizes leading to high erase voltage and slow erase rate
Solution Approach 1:
A silicon nitride layer is introduced as an intermediary protective layer between the TiN floating gate and the HTO oxidation environment. This mediator prevents direct contact between the oxidizing atmosphere and the TiN layer, thereby preventing oxidation while allowing the HTO process to proceed for oxide layer formation.
Solution Approach 2:
The silicon nitride layer creates an inert protective environment for the TiN floating gate during the HTO oxidation process. By establishing this protective barrier, the TiN layer is shielded from oxidizing conditions, maintaining its electrical properties and ensuring reliable erase performance.
2Reliability
If TiN layer is used for floating gate, then good electrical properties are achieved, but oxidation occurs during HTO process affecting structural continuity
Solution Approach 1:
The silicon nitride protective layer is formed preliminarily before the HTO oxidation process begins. This preliminary protective action ensures that the TiN floating gate is already shielded when exposure to oxidizing conditions occurs, preventing oxidation and maintaining structural continuity throughout the manufacturing process.
Solution Approach 2:
The silicon nitride layer serves as a protective intermediary that physically separates the TiN floating gate from the oxidizing HTO environment, preventing direct interaction that would cause oxidation and structural degradation.
3Productivity
If erase gate nesting window is increased, then erase efficiency is improved, but device complexity increases
Solution Approach 1:
The protective structure is segmented into multiple distinct layers (first silicon nitride layer, second silicon nitride layer) with specific functions. This segmentation allows the erase gate nesting window to be enlarged for improved erase efficiency while the distributed protective layers manage the complexity by providing targeted protection at different locations.
Solution Approach 2:
Silicon nitride protective layers are applied locally at critical positions (bottom and sides of the gate trench) rather than uniformly throughout the structure. This local quality approach allows the erase gate nesting window to be optimized for erase efficiency while adding protective functionality only where oxidation risk exists, thereby managing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protective silicon nitride layers effectively prevent oxidation of the TiN layer, resulting in improved erase performance by maintaining the structural integrity and reducing erase voltage, thus enhancing the overall efficiency of the super flash device.
Implementation Method 1
Incorporating a third silicon nitride layer as a protective layer between the second oxide layer and the HTO oxide layer, and a fifth silicon nitride layer to prevent oxidation of the TiN layer during the HTO oxidation process
Data Source
AI summary
The present application discloses a super flash, wherein a device cell includes a first gate trench at the top of a source region, a first spacer structure is formed on a side surface of the first gate trench in a self-aligned manner, and the first spacer structure is formed by means of self-aligned etch of a stack layer of a first tunneling dielectric layer, a floating gate, and a second oxide layer. The material of the floating gate comprises a TiN layer. A second spacer structure is formed on a second side surface of the first spacer structure in a self-aligned manner, and the second spacer structure is formed by means of self-aligned etch of a stack layer of a third silicon nitride layer, a fourth oxide layer, and a fifth silicon nitride layer. The present application further discloses a method for manufacturing a super flash.