Leadless Semiconductor Package with Tin Perimeter Landings
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Solution Overview
Problem
Leadless packaged semiconductor devices, such as QFN devices, face challenges in achieving further compactness due to their design constraints, particularly in reducing the thickness while maintaining reliable electrical connections.
Innovation Solution
The solution involves using perimeter landings made of a material with a mass fraction of tin at least 95%, which are formed through stencil printing and reflowing, and connected to the device die via thin connection lines, allowing for a compact design without the need for conventional lead-frames, and encapsulating these components with a molding compound to ensure structural integrity and electrical insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lead-frame based designs are used, then structural support and electrical connections are provided, but device thickness and overall size increase
Solution Approach 1:
The patent extracts and removes the conventional lead-frame structure from the semiconductor package, retaining only the essential perimeter landings for electrical connection. This elimination of the lead-frame framework enables significant reduction in device thickness while maintaining necessary electrical connectivity through direct bonding wires from the die to the perimeter landings.
Solution Approach 2:
The patent transitions from a three-dimensional lead-frame structure extending vertically to support the die, to a two-dimensional perimeter landing configuration where connections are made at the edges. This dimensional change allows the die to be bonded directly to the substrate without requiring vertical lead extensions, thereby reducing overall device thickness.
2Area of stationary object
If perimeter landings are made smaller to reduce package size, then compactness is improved, but electrical connection reliability deteriorates
Solution Approach 1:
The patent employs composite material structures for the perimeter landings, combining highly conductive materials with appropriate mechanical properties to ensure reliable electrical connections despite reduced size. The use of composite materials allows the landings to maintain electrical integrity while occupying minimal space on the package footprint.
3Length of moving object
If connection lines are made thinner to reduce thickness, then device compactness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements self-aligning features in the bonding process where the bonding wire automatically positions itself relative to the perimeter landing during the bonding operation. This self-service mechanism reduces the stringency of pre-positioning requirements and maintains manufacturing feasibility even with thinner connection lines, as the system compensates for minor positioning variations through its inherent alignment capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of extremely compact semiconductor devices with a thickness as low as 0.05mm to 0.1mm, providing reliable electrical connections and protection from corrosion, while avoiding the limitations of conventional lead-frame based designs.
Implementation Method 1
reflowing the patterned paste material to form a plurality of arranged perimeter landings
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A packaged semiconductor device has a top surface and a bottom surface opposite the top surface. The packaged semiconductor device includes a device die, a plurality of perimeter landings, connection lines, and molding compound. The device die has a first surface and a second surface opposite the first surface. The device die is arranged in a central region of the packaged semiconductor device. The first surface of the device die is arranged towards the bottom surface of the packaged semiconductor device, and the second surface of the device die is arranged towards the top surface of the packaged semiconductor device. The plurality of perimeter landings are exposed on the bottom surface of the packaged semiconductor device and are arranged at perimeter regions of the bottom surface surrounding the device die. The connection lines are connected to the second surface of the device die. Each connection line provides electrical connection between a corresponding connection pad on the second surface of the device die and a corresponding one of the plurality of perimeter landings. The molding compound at least partially encapsulates the device die and the plurality of perimeter landings. The plurality of perimeter landings are made of a material having a mass fraction of tin of at least 95%.