3D Tin-Perovskite TFT Semiconductor Layer for Low-Temperature Mobility

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Solution Overview

Problem

Current thin-film transistors (TFTs) face limitations in charge mobility and are not suitable for high-resolution displays due to low mobility of organic semiconductors or oxide transistors, and inorganic TFTs require high-temperature processes, making them unsuitable for flexible devices on plastic substrates.

Innovation Solution

A thin-film transistor using a semiconductor layer composed of cesium tin triiodide (CsSnI3) or methylammonium tin triiodide (MASnI3) with additives like SnF2, SnBr2, SnI2, SnCl2, PbI2, InI2, and SbI2, formed via low-temperature solution processes such as spin coating or printing, enabling high charge mobility and flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If inorganic thin-film transistors are used to achieve high charge mobility, then charge mobility is improved, but manufacturing complexity increases due to high-temperature processes

Engineering Contradiction:
Improvecharge mobilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent changes the processing temperature parameter from high-temperature (300°C) to low-temperature processes, enabling the formation of inorganic thin-film transistors on plastic substrates while maintaining high charge mobility characteristics

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures including gate insulating films, semiconductor layers, and electrode layers with specific material combinations that enable both high mobility and low-temperature processing compatibility

Inventive Principle:
Principle #40Composite materials

2Speed

If inorganic thin-film transistors are used to achieve high charge mobility, then charge mobility is improved, but adaptability worsens due to incompatibility with plastic substrates

Engineering Contradiction:
Improvecharge mobilityVSAvoidsubstrate compatibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent modifies the temperature parameter to enable processing on temperature-sensitive plastic substrates, achieving adaptability while preserving high charge mobility through optimized low-temperature fabrication processes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent develops a universal transistor structure that can be fabricated on both rigid and flexible substrates using low-temperature processes, making the device adaptable to various application scenarios including flexible displays

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If organic semiconductors are used to enable low-temperature processing, then manufacturing complexity is reduced, but charge mobility deteriorates

Engineering Contradiction:
Improvemanufacturing process complexityVSAvoidcharge mobility
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent uses composite material structures with gate insulating films, semiconductor layers, and electrode layers that collectively achieve both low-temperature processing capability and high charge mobility, overcoming the limitations of individual material types

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS12490459B2Thin film transistor using three-dimensional tin-based perovskite as a semiconductor layer and preparation method thereof
Publication Date: 2025.12.02 POSTECH ACADEMY INDUSTRY FOUNDATION
  • US12490459B2 patent drawing
  • US12490459B2 patent drawing
  • US12490459B2 patent drawing

AI summary

Disclosed is a thin-film transistor including a substrate including a gate electrode formed thereon, a gate insulating film disposed on an entire face of the substrate, a semiconductor layer disposed on an entire face of the gate insulating film, and source and drain electrodes disposed on the semiconductor layer so as to be spaced apart from each other, wherein the semiconductor layer includes cesium tin triiodide (CsSnI3) or methylammonium tin triiodide (MASnI3), wherein the semiconductor layer further contains an additive.