Multiple TiN Work Function Layers With Reduced Etch Damage

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Solution Overview

Problem

Existing methods for fabricating transistor gates with multiple work function layers cause damage to the TiN layers due to excessive etching, leading to electrical drift and yield loss.

Innovation Solution

A method involving sequential deposition and selective removal of TiN layers with decreasing thicknesses, using photolithography and etching, to minimize etchant damage, ensuring each subsequent etching step has a smaller etching amount than the previous one.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple TiN layers are removed through photolithography and etching to achieve different work functions, then transistor gates with different work functions are formed, but the TiN layers are damaged by excessive etching

Engineering Contradiction:
Improvework function differentiationVSAvoidTiN layer integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by depositing a protective layer (such as silicon nitride or silicon oxide) on the TiN layers before the etching process. This protective layer is deposited in advance to prevent direct contact between the etchant and the TiN layers, thereby preserving their integrity while still allowing selective removal to achieve different work functions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary protective layer that acts as a mediator between the etchant and the TiN layers. This intermediate layer allows the etching process to proceed selectively for work function differentiation while protecting the TiN layers from damage, thus resolving the contradiction between versatility and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If strong etching is used to remove TiN layers efficiently, then the fabrication process is faster, but the TiN layers in the junction area are seriously damaged

Engineering Contradiction:
Improveetching efficiencyVSAvoidTiN layer quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The protective layer is deposited in advance before the etching process, enabling the use of stronger etchants that can efficiently remove TiN layers without directly damaging them. The protective layer absorbs the harsh etching conditions, allowing high productivity while maintaining manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the potentially harmful strong etching process into a beneficial efficient removal process by introducing the protective layer. The strong etchant that would normally damage the TiN layers is now used efficiently to remove material where needed, while the protective layer prevents damage, thus turning a harmful factor into a benefit for productivity.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents damage to TiN layers by controlling etching amounts, maintaining electrical integrity and improving yield in transistor gate fabrication.

Implementation Method 1

forming four or more TiN layers with different thicknesses through atomic layer deposition (ALD)

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

removing the first work function layer above the first to the (n−1)th transistor gates through photolithography and etching

Methodology Applied
Scientific EffectPhotolithography: Photography

Data Source

PatentUS12588442B2Method for fabricating multiple work function layers
Publication Date: 2026.03.24 SHANGHAI HUALI INTEGRATED CIRCUIT CORP
  • US12588442B2 patent drawing
  • US12588442B2 patent drawing
  • US12588442B2 patent drawing

AI summary

The present application provides a method for fabricating multiple work function layers, including: forming the first to the nth transistor gates with notches; forming a blocking layer in the notches; depositing the first work function layer and removing the first work function layer on the first to the (n−1)th transistor gates; depositing a second work function layer; removing the second work function layer on the first to the (n−2)th transistor gates; depositing a third work function layer on the blocking layer on the first to the (n−2)th transistor gates and the second work function layer on the (n−1)th and nth transistor gates; removing the third work function layer on the first to (n−3)th transistor gates; depositing the third to the (n−1)th work function layers by analogy until only the blocking layer exists on the last transistor gate, herein the thickness of the third to the (n−1)th work function layers decreases sequentially and gradually.