Tined Gate for Threshold Voltage Control in Piezoelectric Transistors
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Solution Overview
Problem
Conventional heterojunction field effect transistors (HFETs) are typically 'normally on' devices, which is undesirable for power electronics due to safety and design reasons, and existing methods to change the threshold voltage increase device complexity and cost.
Innovation Solution
A tined gate structure is introduced, where the gate has a main body and multiple tines, with the tines' proximal ends connected to the main body, middle portions projecting through gaps, and distal ends separated from the piezoelectric layer, allowing for a shift in threshold voltage without significantly increasing complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If recessed-gate structure is used to increase threshold voltage, then threshold voltage increases, but fabrication complexity increases and gate leakage increases
Solution Approach 1:
The gate electrode is segmented into multiple tines that extend through the dielectric layer, creating discrete conductive regions. This segmentation allows selective application of electric field to different channel regions, enabling threshold voltage control without requiring complex recessed gate fabrication. The tines are formed by simple patterned deposition processes rather than complex etching and cleaning steps.
Solution Approach 2:
The gate structure extends into the vertical dimension by projecting tines through the dielectric layer, rather than relying on horizontal recessed gate structures. This vertical extension allows the gate to influence the channel potential at multiple depths, effectively controlling threshold voltage without requiring complex lateral recesses that increase fabrication difficulty.
2Manufacturing precision
If piezo neutralization layer is added to improve threshold voltage uniformity, then threshold voltage uniformity improves, but fabrication complexity and cost increase significantly
Solution Approach 1:
The tined gate structure itself generates the electric field needed to control threshold voltage uniformly across the channel. The multiple tines create overlapping electric field regions that self-adjust to provide uniform potential distribution, eliminating the need for separate piezo neutralization layers. The structure serves its primary gating function while simultaneously achieving uniform threshold voltage control.
3Reliability
If plasma treatment and Si3N4 deposition are used to increase threshold voltage, then threshold voltage increases, but device damage increases and fabrication complexity increases
Solution Approach 1:
The patent replaces plasma treatment (a chemical/physical process that causes damage) with a purely structural electric field approach. The tined gate geometry creates the necessary electric field distribution through its physical configuration alone, eliminating the need for damaging plasma exposure and complex multi-step deposition processes.
4Reliability
If p-AlGaN gate is used to increase threshold voltage through hole injection, then threshold voltage increases, but fabrication complexity and cost increase
Solution Approach 1:
Instead of changing material composition (p-AlGaN doping), the patent achieves threshold voltage control by changing geometric parameters of an n-type or intrinsic gate. The tine dimensions, spacing, and depth are optimized to create the desired electric field distribution, allowing threshold voltage adjustment through geometric design rather than complex doping and material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tined gate structure effectively changes the threshold voltage, making the device 'normally off' with a positive threshold voltage, reducing gate capacitance and minimizing punch-through current, while maintaining low fabrication complexity and cost.
Implementation Method 1
a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.