TiN FinFET Gate Layout to Reduce Metal Boundary Effect

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Solution Overview

Problem

Current techniques for manufacturing 14 nm FinFETs are prone to the metal boundary effect (MBE) due to titanium nitride (TiN) undercut at the side bottom of fins, particularly affecting P-type SRAMs, leading to a decrease in threshold voltage.

Innovation Solution

A method involving sequential arrangement of fin structures with strategic deposition and removal of TiN layers to mitigate the metal work function boundary effect, ensuring continuous coverage and minimizing undercut, thereby maintaining or increasing the threshold voltage of P-type SRAMs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TiN layer is deposited to cover the fin structures, then the metal boundary effect is intensified, but the threshold voltage of P-type SRAM decreases

Engineering Contradiction:
Improvemetal boundary effectVSAvoidthreshold voltage
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The TiN layer is divided into multiple segments (first TiN layer, second TiN layer, third TiN layer) with different coverage patterns. Each segment is selectively deposited and removed in specific regions to achieve precise control over the metal boundary effect while maintaining threshold voltage stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the fin structures receive different TiN layer treatments. The first TiN layer is removed from above the third fin structure and partially from between second and third fin structures. The second TiN layer is removed from the second fin structure. This local differentiation allows optimization of metal boundary effect in specific areas without compromising overall device performance.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If TiN layer is continuously deposited to prevent undercut, then the metal boundary effect is reduced, but the device complexity increases

Engineering Contradiction:
ImproveundercutVSAvoidprocess steps
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The first TiN layer is deposited preliminarily across all fin structures before selective removal. This preliminary deposition ensures complete coverage to prevent undercut, followed by selective removal in subsequent steps to achieve the desired pattern without requiring complex simultaneous deposition processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Multiple TiN layers are nested sequentially (first TiN layer, then second TiN layer, then third TiN layer), where each layer builds upon the previous one. This nested approach allows complex patterning to be achieved through simple sequential deposition and removal steps rather than complex single-step processes.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method reduces the TiN layer thickness at the bottom edge of P-type transistor fins, minimizing undercut and metal boundary effects, which helps in maintaining or increasing the threshold voltage of P-type SRAMs.

Implementation Method 1

depositing a first TiN layer simultaneously on the first to fourth fin structures

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS11756798B2Method for improving metal work function boundary effect
Publication Date: 2023.09.12 SHANGHAI HUALI INTEGRATED CIRCUIT CORP
  • US11756798B2 patent drawing
  • US11756798B2 patent drawing
  • US11756798B2 patent drawing

AI summary

The present application provides a method for improving the metal work function boundary effect in FinFET process, the method comprises steps of: depositing a first TiN layer on four fin structures. The first TiN layer has no gap between the second and the third fin structures; removing the first TiN layer up to a first distance from the midline between the second and third fin structures at the second fin structure side; depositing a second TiN layer; removing the second and first TiN layers from second fin structure. The thickness of the TiN layer at the bottom edge of the fin structure at the later structure of the ultra-low threshold voltage P-type transistor will be smaller from this process. Thus formed TiN layer is less prone to a bottom undercut during etching, thereby reducing the metal boundary effect and increasing of the threshold voltage of the device.