Tiny RFID Die Layout for IC Authentication Without Area Penalty
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Solution Overview
Problem
The widespread adoption of integrated circuits (ICs) has led to the rise of counterfeit ICs, posing significant threats to the electronics industry, economy, and public safety, necessitating the development of anti-counterfeiting measures, particularly through tiny RFID tags embedded in ICs to ensure authenticity and functionality.
Innovation Solution
The integration of a tiny RFID tag, less than 0.1 mm² in area, primarily digital and utilizing dual-phase RF-only logic, embedded in ICs, which can be manufactured using portable digital IP blocks and shared power supply transistors, with data encoded at the foundry, enabling secure authentication and unlocking device capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RFID technology is incorporated into ICs to enhance anti-counterfeiting measures, then authentication reliability is improved, but device area increases
Solution Approach 1:
The patent merges the RFID tag with the IC by embedding the RFID tag directly into the IC substrate, creating a unified structure where the RFID tag and IC share the same physical space and power supply infrastructure, thereby minimizing area overhead while maintaining authentication functionality
Solution Approach 2:
The IC is designed to serve multiple functions: it acts as both the main integrated circuit for device operation and as the host for the embedded RFID tag for authentication purposes, eliminating the need for separate dedicated authentication hardware and reducing overall device area
2Area of moving object
If the RFID tag area is reduced to less than 0.1 mm², then device miniaturization is achieved, but manufacturing complexity increases
Solution Approach 1:
The RFID tag is segmented into minimal essential components that can be implemented using standard foundry process blocks, allowing the tiny RFID tag to be manufactured using existing CMOS fabrication processes without requiring specialized or complex manufacturing steps
Solution Approach 2:
The patent employs parameter changes in the RFID tag design, including using dual-phase RF-only logic and shared power supply transistors, to reduce the tag's area to less than 0.1 mm² while maintaining functionality through optimized electrical characteristics and compact circuit topology
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides reliable and efficient authentication of ICs, preventing counterfeit usage and ensuring device safety and security by verifying RFID data against predefined criteria, applicable in various fields requiring security and access control.
Implementation Method 1
Radio-Frequency Identification (RFID) technology that allows for the identification and tracking of objects using radio waves
Data Source
AI summary
A method of enabling a capability of an electronic device includes interrogating, with a radio frequency reader, a passive wireless identifier that is embedded within and shares a power grid with logic circuitry of an integrated circuit die present in the electronic device. The passive wireless identifier occupying no more than about 0.1 mm2 of die area. Identifier data is received from the passive wireless identifier. The method also includes verifying that the identifier data satisfies predetermined unlock criteria. The capability of the electronic device is enabled in response to the verifying.