Tipless Epitaxial Source/Drain Regions for Higher Channel Strain
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Solution Overview
Problem
The existing methods for forming strain-inducing source/drain regions in semiconductor devices, such as PMOS-FETs, are limited by the need for gate isolation spacers, which restrict the location and effectiveness of the strain-inducing regions, thereby limiting the enhancement of hole mobility.
Innovation Solution
The formation of tipless epitaxial source/drain regions directly adjacent to the gate stack, without the need for gate isolation spacers, by using a dielectric gate stack placeholder in a replacement gate integration scheme, allowing for increased strain-inducing ability and proximity to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate isolation spacers are used to form strain-inducing source/drain regions, then material growth on gate electrode is inhibited, but the location and effectiveness of strain-inducing regions are restricted
Solution Approach 1:
The patent removes gate isolation spacers from the fabrication process entirely. Instead of using spacers to define the location of strain-inducing source/drain regions, the invention directly forms these regions adjacent to the gate stack, extracting the spacer component and its associated limitations from the process.
Solution Approach 2:
The patent performs preliminary formation of strain-inducing source/drain regions before final gate stack completion. By using a dielectric placeholder during intermediate stages and removing it later, the strain-inducing regions can be formed in optimal locations without the constraints of final gate isolation structures.
2Speed
If strain-inducing source/drain regions are formed closer to the channel region, then hole mobility enhancement is improved, but parasitic resistance control becomes more challenging
Solution Approach 1:
The patent applies different material compositions and doping profiles to different regions of the source/drain structures. Strain-inducing regions are formed with specific lattice-matched materials to maximize hole mobility in the channel interface, while other regions are optimized for electrical contact and low resistance, allowing simultaneous optimization of both mobility and parasitic resistance.
Solution Approach 2:
The patent employs composite source/drain structures combining multiple materials with different properties. For example, silicon-germanium alloys are used to induce strain in the channel while maintaining appropriate electrical characteristics, and doped regions are engineered with specific concentration gradients to balance mobility enhancement with resistance control.
3Device complexity
If tip extensions are added to reduce parasitic resistance, then electrical performance is improved, but the lattice mismatch strain on channel region is reduced
Solution Approach 1:
The patent segments the source/drain structure into functionally distinct regions: strain-inducing regions that maintain lattice mismatch with the channel for mobility enhancement, and contact regions that provide low-resistance electrical connections. This segmentation eliminates the need for tip extensions while preserving both strain and electrical performance.
Solution Approach 2:
The patent extends strain-inducing regions in the vertical dimension by forming them as deeply recessed structures that undercut the gate stack. This three-dimensional configuration allows strain-inducing material to be positioned closer to the channel interface without requiring horizontal tip extensions, thereby maintaining lattice mismatch strain while achieving low parasitic resistance through improved contact geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mobility of charge-carriers in the channel region by increasing the strain-inducing ability of the source/drain regions, while eliminating the need for tip extensions and reducing parasitic resistance.
Implementation Method 1
strain-inducing source/drain regions are formed by selectively growing an epitaxial film into recessed regions
Implementation Method 2
The lattice constant of the epitaxial silicon/germanium film is greater than that of crystalline silicon by a factor of ~1% (for 70% Si, 30% Ge) and so strain-inducing source/drain regions are comprised of a material with a larger lattice constant than that of channel region 102. Therefore, a uniaxial compressive strain, depicted by the arrows in FIG. 1C, is rendered on channel region 102
Data Source
AI summary
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.