Tipless Transistors for Integrated Circuits
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Solution Overview
Problem
Conventional integrated circuits with shrinking transistor sizes face performance issues due to 'short-channel' effects, such as drain-induced barrier lowering, which arise from depletion regions created by source-drain diffusions, leading to inefficiencies in transistor performance.
Innovation Solution
The development of tipless transistors with vertical doping profiles that do not include lateral source and drain extensions under the gate electrode, along with the use of deeply depleted channel (DDC) transistors that incorporate a screening region and a threshold voltage set region to manage depletion regions and enhance body coefficient precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor channel size is decreased to improve integration density, then productivity increases, but short-channel effects worsen and transistor performance deteriorates
Solution Approach 1:
The patent transitions from conventional planar transistors to three-dimensional FinFET structures. By verticalizing the channel through fin formation, the effective channel length is extended in the vertical dimension while maintaining a small lateral footprint. This allows continued scaling for higher integration density while preserving transistor performance by reducing short-channel effects through improved gate control in the vertical dimension.
Solution Approach 2:
The patent implements selective doping regions including lightly-doped drain (LDD) extensions and halo implants in specific locations within the transistor structure. These localized doping variations create optimal electric field distributions that suppress short-channel effects in critical regions while maintaining overall device performance and enabling continued scaling.
2Reliability
If source and drain extensions are added to reduce short-channel effects, then transistor performance improves, but device complexity increases
Solution Approach 1:
The patent combines multiple doping functions into integrated processing steps. The lightly-doped drain extensions and halo doping regions are formed through coordinated implantation sequences that achieve both short-channel effect suppression and threshold voltage control in a unified device structure, reducing the need for separate complex structures while maintaining performance benefits.
3Ease of manufacture
If conventional doping methods are used, then manufacturing process is simple, but dopant migration occurs and threshold voltage precision deteriorates
Solution Approach 1:
The patent performs preliminary doping actions during specific process stages where dopant migration can be controlled. By establishing doping profiles before subsequent high-temperature processing steps, the patent prevents excessive dopant diffusion that would otherwise occur, thereby maintaining precise threshold voltage control while using conventional doping equipment and processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved transistor performance by reducing dopant migration, enhancing threshold voltage precision, and minimizing short-channel effects, resulting in better control over depletion zones and reduced threshold voltage variation, thereby improving overall circuit efficiency.
Implementation Method 1
Some short-channel effects, such as drain-induced barrier lowering, can arise from depletion regions created by the source-drain diffusions
Implementation Method 2
improved transistor performance by reducing dopant migration
Data Source
AI summary
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.