TISA-Based Dual Processor System Testing
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Solution Overview
Problem
Existing system testing approaches, such as JTAG and IJTAG, are limited by their inability to perform interactive testing, lack of knowledge about the system under test, and proprietary implementation-dependent methods, which restricts the complexity of operations and requires offline examination of testing results.
Innovation Solution
The introduction of a Test Instruction Set Architecture (TISA) that combines computer science capabilities with system testing, allowing for finer-grain control and interactive testing by adapting a software-based instruction set architecture to generate test instructions that can be executed via a Test Access Port (TAP), enabling remote and interactive testing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single processor is used to execute both test control instructions and TAP access instructions, then the device complexity is reduced, but the testing productivity and interactivity are limited because the processor must sequentially handle all instructions
Solution Approach 1:
The testing system divides the processor functionality into two separate processors: a first processor dedicated to executing test control instructions and a second processor dedicated to accessing the TAP. This segmentation allows parallel execution of different instruction types, improving testing productivity while maintaining manageable device complexity through clear functional separation.
Solution Approach 2:
The first processor is designed with the capability to detect and identify TAP access instructions within the stream of test control instructions. This multi-functionality allows the first processor to handle both test control and TAP access instruction recognition, while the actual TAP access is performed by the second processor, optimizing the overall system architecture.
2Ease of operation
If existing JTAG/IJTAG standards are used, then the ease of operation is maintained through standardized interfaces, but the ability to perform interactive testing and sophisticated data processing is lost
Solution Approach 1:
The system separates test control functionality from TAP access functionality into two distinct processors. This allows the first processor to execute complex test control instructions with full interactive capabilities while the second processor handles standardized TAP access, combining the versatility of custom control with the ease of standardized interfaces.
Solution Approach 2:
The first processor acts as an intermediary between the control system and the TAP. It detects TAP access instructions in the instruction stream and routes them to the second processor for execution, enabling sophisticated interactive testing while maintaining compatibility with standardized TAP interfaces.
3Productivity
If test instructions are executed sequentially without parallel processing, then the device complexity is minimized, but the testing time and productivity are reduced
Solution Approach 1:
The testing system implements parallel processing by segmenting the instruction execution into two independent processor units. The first processor executes test control instructions while the second processor simultaneously accesses the TAP, enabling concurrent operation and significantly improving testing speed without requiring complex multi-core architectures.
Data Source
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AI summary
An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.