Selective TiSi2 Source/Drain Contacts for Low-Resistance FETs
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Solution Overview
Problem
Conventional FinFET manufacturing processes face challenges such as source/drain damage, etch stop layer residuals, and thermal budget limitations, leading to poor quality contacts and uncontrolled variations in electrical performance.
Innovation Solution
A method for manufacturing FET semiconductor structures involves selectively depositing a TiSi2 film with a C54 structure directly on and fully covering the source/drain contacts, followed by replacing the dummy gate with a replacement metal gate, thereby improving interface quality and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form TiSi2 on source/drain contacts, then the process is simpler, but source/drain damage and etch stop layer residuals occur leading to poor contact quality
Solution Approach 1:
The dummy gate is formed beforehand to serve as a protective mask during selective TiSi2 deposition. This preliminary structure enables precise control of where TiSi2 forms (only on source/drain contacts) while preventing damage to the source/drain regions and removing etch stop layer residuals, thus improving contact quality without excessive process complexity
Solution Approach 2:
The dummy gate acts as an intermediary element that facilitates selective deposition. By introducing this temporary structure, the process achieves precise spatial control of TiSi2 formation, improving contact quality. The dummy gate is later removed and replaced, so its temporary presence enables the beneficial outcome without permanent added complexity
2Manufacturing precision
If thermal budget is increased to improve TiSi2 formation, then contact quality improves, but device performance varies due to thermal budget limits
Solution Approach 1:
The selective deposition process applies different thermal treatments to different regions: source/drain contacts receive sufficient thermal energy for high-quality TiSi2 formation, while the rest of the device structure is protected from excessive heating. This local differentiation allows optimal contact quality without compromising overall device performance consistency
Solution Approach 2:
The process changes the deposition parameters (temperature, pressure, gas composition) to enable selective TiSi2 formation at controlled conditions. By carefully controlling these parameters during the deposition process, high-quality contacts are formed without exceeding thermal budget limits that would cause device performance variations
3Area of moving object
If contact area is reduced for device scaling, then device density increases, but contact resistance increases due to reduced contact area
Solution Approach 1:
A composite contact structure is formed with TiSi2 (low resistance silicide layer) combined with copper or cobalt (low resistance metal layer). This composite structure compensates for the reduced contact area by providing excellent electrical conductivity, thus maintaining low contact resistance even as contact dimensions are scaled down for higher device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a one-step wrap-around TiSi2 film formation, improving interface quality, reducing contact resistance, and mitigating thermal budget concerns, resulting in enhanced device performance.
Implementation Method 1
A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact
Implementation Method 2
exposing the substrate to a process gas including a titanium-containing precursor gas and a silicon-containing precursor gas
Implementation Method 3
maintaining a substrate temperature between about 700° C. and about 800° C.
Data Source
AI summary
A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.