Fluorine-Free Titanium Contact Interface for Semiconductor Gates
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Solution Overview
Problem
During the manufacturing of semiconductor devices like logic devices or SRAMs, fluorine-based gases used in pre-clean chambers leave behind residual fluorine layers, increasing contact resistance between metal and poly layers, which degrades device performance.
Innovation Solution
An in-situ high-temperature anneal process using a degas chamber at temperatures above 300°C to vaporize and remove the fluorine residual layer, followed by forming titanium or titanium nitride layers to create a silicide layer, thereby establishing a fluorine-free interface between the metal gate and the metal on poly layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fluorine-based gases are used in pre-clean chambers to remove oxide layers, then oxide removal effectiveness is improved, but residual fluorine layer forms on metal gate increasing contact resistance
Solution Approach 1:
The patent extracts and removes the harmful fluorine residual layer from the metal gate surface using a separate removal process after the pre-clean operation. This separates the oxide removal function from the fluorine contamination problem, allowing effective oxide removal while eliminating the harmful residual fluorine that causes increased contact resistance.
Solution Approach 2:
The patent introduces an intermediary removal process (using ammonia-based solutions or plasma treatment) between the fluorine-based pre-clean step and subsequent metal layer formation. This intermediary step mediates by converting or removing the fluorine residual layer without affecting the underlying metal gate, thereby reducing contact resistance while preserving oxide removal benefits.
2Ease of manufacture
If residual fluorine layer remains on metal gate, then pre-clean process simplicity is maintained, but device performance degrades due to increased contact resistance
Solution Approach 1:
The patent applies a preliminary fluorine removal treatment (using ammonia-based solutions or plasma) immediately after the fluorine-based pre-clean process and before metal layer deposition. This preliminary action prevents fluorine contamination from affecting subsequent processing steps and device performance, while maintaining the overall simplicity of the manufacturing flow.
3Object-affected harmful factors
If high temperature anneal process is applied to remove fluorine residual layer, then contact resistance is reduced, but processing complexity increases
Solution Approach 1:
The patent changes the chemical parameters of the removal process by using ammonia-based solutions or plasma treatment instead of high temperature thermal processing. This parameter change allows fluorine removal at lower temperatures and simpler process conditions while achieving the same goal of reducing contact resistance, thereby avoiding increased processing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact and metal resistance, enhancing the performance of semiconductor devices by eliminating the adverse effects of fluorine residual layers.
Implementation Method 1
An in-situ high-temperature anneal process using a degas chamber at temperatures above 300°C to vaporize and remove the fluorine residual layer
Implementation Method 2
forming titanium or titanium nitride layers on the sidewalls and the bottoms of the trenches to cause a silicide layer to form on the epitaxial source/drain
Data Source
AI summary
A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.