Titanium Contact Liner on pFET Source/Drain Regions
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Solution Overview
Problem
In advanced CMOS devices, particularly at 20 nm and 14 nm technology nodes, metal semiconductor alloy contact resistance contributes significantly to total parasitic resistance, necessitating a reduction in source/drain metal contact resistance for improved performance.
Innovation Solution
A semiconductor structure with non-metal semiconductor alloy contact structures for FETs, featuring a highly doped epitaxial semiconductor material directly contacting the source/drain regions, a titanium liner, a diffusion barrier liner, and a contact metal portion, which reduces contact resistance without the need for metal semiconductor alloy formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal semiconductor alloy contacts are formed on source/drain regions, then contact resistance is reduced, but material consumption increases and process complexity increases
Solution Approach 1:
The patent extracts the problematic metal semiconductor alloy formation step from the contact structure fabrication process. Instead of forming metal-semiconductor alloys, the invention uses a titanium liner directly on highly doped epitaxial semiconductor material, eliminating the need for silicidation or other alloy formation processes while maintaining low contact resistance.
Solution Approach 2:
The patent changes the doping concentration parameter of the epitaxial semiconductor material to achieve highly doped regions (greater than 1E19 atoms/cm³). This parameter change enables the semiconductor material itself to provide low contact resistance when contacted by titanium, replacing the need for metal-semiconductor alloy formation.
2Reliability
If metal semiconductor alloy contacts are formed on source/drain regions, then contact resistance is reduced, but device complexity increases
Solution Approach 1:
The patent removes the complex metal semiconductor alloy formation process from the fabrication sequence. The simplified approach deposits titanium liner and fill metal directly onto highly doped epitaxial regions, eliminating silicidation steps, alloy annealing processes, and associated process control complexities.
Solution Approach 2:
Instead of forming metal-semiconductor alloys by combining metal and semiconductor materials, the invention inverts the approach by using highly doped semiconductor material as the contact region itself, contacted by a titanium liner. This reverses the traditional metal-first approach to a semiconductor-doped-region-first approach.
3Reliability
If highly doped epitaxial semiconductor material is used with titanium liner, then contact resistance is reduced and material consumption is eliminated, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes specific parameter ranges for the epitaxial semiconductor material doping concentration (greater than 1E19 atoms/cm³) to ensure low contact resistance. By controlling the doping parameter during epitaxial growth, the process achieves reliable electrical contact properties while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively lowers contact resistance, enhancing the performance of FETs by reducing parasitic resistance and eliminating material consumption in FinFET and other semiconductor devices.
Implementation Method 1
an epitaxial semiconductor material of a second dopant concentration that is greater than the first dopant concentration directly contacting a topmost surface of the source region or the drain region
Implementation Method 2
epitaxial semiconductor material of a second dopant concentration that is greater than the first dopant concentration
Implementation Method 3
a diffusion barrier liner located on the titanium liner
Data Source
AI summary
A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.


