Titanium Nitride Barrier Seed Layer for Low-Resistance Interconnects

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Narrower vertical interconnects in semiconductor devices increase electrical resistance, leading to higher heat generation and device failure risks due to the significant effect of resistive layers on overall resistivity.

Innovation Solution

A dual-damascene interconnect structure is fabricated using a titanium nitride layer that acts as both a barrier and seed for conductive materials like tungsten or poly-silicon, allowing the conductive material to fill the trench completely, reducing resistivity and enabling narrower interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If narrower vertical interconnects are used to reduce chip area, then the amount of chip real-estate used by electrical connections is reduced, but the electrical resistance of the interconnect increases significantly

Engineering Contradiction:
Improvechip real-estateVSAvoidelectrical resistance
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent combines the barrier layer and seed layer into a single integrated layer structure. The barrier layer is formed with a gradient composition where one portion has high barrier properties and another portion has high seed properties, merging the functions of both layers into a unified structure that reduces total layer thickness and overall resistance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The barrier layer is designed with non-uniform composition where different portions have different properties. One portion is optimized for barrier functionality while another portion is optimized for seed functionality, allowing each region to perform its specific function efficiently without compromising the other.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If narrower vertical interconnects are used to reduce chip area, then more circuit components can be fabricated within a given area, but heat generation increases due to higher resistance

Engineering Contradiction:
Improvechip real-estateVSAvoidheat generation
Core Design Contradiction:
Area of stationary objectVSTemperature

Solution Approach 1:

The integrated barrier/seed layer structure reduces the total thickness of resistive layers, thereby reducing the overall resistance of the interconnect. This reduction in resistance directly decreases I²R heating, allowing narrower interconnects to operate at lower temperatures.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If narrower vertical interconnects are used to reduce chip area, then more circuit components can be fabricated within a given area, but the likelihood of device failure increases

Engineering Contradiction:
Improvechip real-estateVSAvoiddevice failure likelihood
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The unified barrier/seed layer structure provides both barrier and seed functions in a single integrated layer, ensuring proper conductive material growth while preventing electrical and chemical interactions with surrounding dielectric. This dual functionality in one layer reduces the risk of defects and device failure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

By optimizing different portions of the barrier layer for specific functions (barrier vs. seed), the structure ensures reliable conductive material growth and proper interface formation, reducing the likelihood of interconnect failure in narrow structures.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in lower resistance interconnects, reducing heat generation and device failure risks while allowing for more compact and efficient semiconductor device design.

Implementation Method 1

a barrier layer used to prevent electrical and chemical interactions between the conductive interconnect and the surrounding dielectric

Methodology Applied
Scientific EffectBarrier layer:

Implementation Method 2

a seed layer used to promote the growth of the conductive metal within the interconnect

Methodology Applied
Scientific EffectSeed layer:

Implementation Method 3

allowing the conductive material to fill the trench completely, reducing resistivity

Methodology Applied
Scientific EffectConductive material deposition:

Data Source

PatentUS9202786B2Low-resistance interconnects and methods of making same
Publication Date: 2015.12.01 MICRON TECHNOLOGY INC
  • US9202786B2 patent drawing
  • US9202786B2 patent drawing
  • US9202786B2 patent drawing

AI summary

Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.