Titanium Silicide Liner for DRAM Contact Resistance
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Solution Overview
Problem
In DRAM semiconductor memory devices, reducing bit line pitch increases bit line capacitance due to the silicon layer, leading to higher contact resistance as the bit line becomes thinner, necessitating a full metal structure without a silicon layer to maintain effective contact with the source/drain region.
Innovation Solution
The semiconductor device incorporates a titanium silicide layer extending from the contact plug to the interlayer dielectric, with a metal silicide layer forming a cup shape around a conductive material, ensuring a larger contact area and reducing contact resistance between the barrier metal and the bit contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bit line pitch is reduced to decrease memory cell size, then the integration density is improved, but the bit line capacitance is increased due to the silicon layer
Solution Approach 1:
The patent removes the silicon layer from the bit line structure, extracting the problematic capacitive element while retaining the essential conductive function through a full metal structure with barrier metal and metal silicide layers
Solution Approach 2:
The patent employs a composite material structure consisting of barrier metal (TiN), metal silicide (TiSi2), and metal layers (W) to replace the traditional silicon-containing bit line, achieving both low capacitance and effective contact properties
2Loss of energy
If the bit line is made thinner to reduce capacitance, then the energy loss is reduced, but the contact area between the contact plug and bit line is reduced, increasing contact resistance
Solution Approach 1:
The metal silicide layer extends vertically from the contact plug interface up through the interlayer dielectric to the bit line, adding a vertical dimension to the contact area that compensates for the reduced horizontal contact area in thinner bit lines
Solution Approach 2:
The multi-layer composite structure with barrier metal, metal silicide, and metal layers creates multiple interfaces and a cup-shaped configuration that increases the effective contact area and reduces contact resistance despite reduced bit line thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces contact resistance and maintains a sufficient connection area, ensuring efficient conductivity even as bit line thickness decreases, supporting the integration of smaller memory cell sizes in DRAM devices.
Implementation Method 1
a metal silicide layer is formed on its interface in order to reduce a contact resistance between the barrier metal (TiN) and silicon
Implementation Method 2
a first metal silicide comprising a cup shape including a bottom portion facing to the substrate
Data Source
AI summary
Disclosed herein is a device that includes a substrate, a contact plug disposed on the substrate, an interlayer dielectric over the substrate to define the contact plug, a titanium silicide extending continuously from an upper portion of the contact plug to over the interlayer dielectric, a conductive material disposed over the titanium silicide.