Redistribution Structure Adhesion Layer for TIV Shadow Delamination

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Solution Overview

Problem

Delamination between redistribution layers (RDLs) and polymer layers in semiconductor device packages occurs due to thermal expansion, leading to increased risk of electrical shorting and package failures, reducing yield.

Innovation Solution

An adhesion layer is formed over portions of the RDLs located in the shadow of through insulator vias (TIVs) to increase adhesion between RDLs and polymer layers, encapsulating them and reducing the likelihood of delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through insulator vias (TIVs) are formed in the redistribution structure, then electrical connectivity is achieved, but thermal expansion stress causes delamination between RDLs and polymer layers

Engineering Contradiction:
Improveelectrical connectivityVSAvoidadhesion between RDL and polymer layer
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

An adhesion layer is introduced as an intermediary between the RDL and polymer layer. This adhesion layer specifically addresses the interface where delamination occurs due to TIV-induced thermal stress, serving as a mediator that maintains both electrical connectivity through TIVs and structural stability by preventing delamination at the RDL-polymer interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The adhesion layer is applied locally at specific interfaces where delamination risk is highest - namely between RDLs and polymer layers in the shadow regions of TIVs. This localized application targets the precise areas experiencing maximum thermal stress concentration, rather than applying uniformly across the entire structure, thereby resolving the contradiction between maintaining connectivity and preventing localized delamination.

Inventive Principle:
Principle #3Local quality

2Stability of the object's composition

If adhesion layer is formed over RDL portions in TIV shadow regions, then delamination risk is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improveadhesion between RDL and polymer layerVSAvoidmanufacturing process complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The adhesion layer is strategically applied only in specific shadow regions of TIVs where delamination stress is concentrated, rather than covering the entire RDL surface. This localized approach reduces the overall complexity of the manufacturing process compared to a full-coverage adhesion layer, while still effectively addressing the delamination problem in the most critical areas.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The adhesion layer effectively reduces the risk of delamination and electrical shorting, enhancing the reliability and yield of semiconductor device packages by mitigating the impact of thermal stress from TIVs.

Implementation Method 1

An adhesion layer is formed over portions of the RDLs located in the shadow of through insulator vias (TIVs) to increase adhesion between RDLs and polymer layers

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

thermal expansion that is caused by one or more semiconductor processing operations that are performed after the redistribution structure is formed. For example, thermal expansion of a through insulator layer via (TIV) can result from high temperatures in a ball grid array (BGA) ball mounting reflow operation

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20240038649A1Semiconductor device package and methods of formation
Publication Date: 2024.02.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240038649A1 patent drawing
  • US20240038649A1 patent drawing
  • US20240038649A1 patent drawing

AI summary

An adhesion layer may be formed over portions of a redistribution layer (RDL) in a redistribution structure of a semiconductor device package. The portions of the RDL over which the adhesion layer is formed may be located in the “shadow” of (e.g., the areas under and/or over and within the perimeter of) one or more TIVs that are connected with the redistribution layer structure. The adhesion layer, along with a seed layer on which the portions of the RDL are formed, encapsulate the portions of the RDL in the shadow of the one or more TIVs, which promotes and/or increases adhesion between the portions of the RDL and the polymer layers of the redistribution structure.