Semiconductor Package TIV Shallow Trench ICP Etching
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in achieving smaller pitch I/O bumps with high critical dimension uniformity and low overlay shift, leading to manufacturing errors and increased costs due to the need for larger area enclosures and laser drill operations.
Innovation Solution
The introduction of a shallow trench in the polymer layer with a tapered sidewall for forming I/O bumps, where a seed layer is placed between the trench and the I/O bump, allowing for smaller pitch I/O bumps and improved solder-I/O bump joint strength through a manufacturing method involving lithography and dry etching instead of laser drilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional laser drill operations are used to form I/O bumps, then manufacturing process is simpler, but critical dimension uniformity deteriorates and overlay shift increases
Solution Approach 1:
The patent replaces the mechanical laser drilling process with a chemical etching process using inductively coupled plasma (ICP). This substitution eliminates the mechanical limitations of laser drilling, achieving superior critical dimension uniformity and reduced overlay shift through controlled chemical reactions rather than mechanical ablation.
Solution Approach 2:
The patent changes the fundamental process parameters from thermal-mechanical (laser drilling) to chemical-plasma (ICP etching). By adjusting plasma power, gas flow rates, and etch chemistry, the process achieves precise control over I/O bump dimensions, resulting in improved critical dimension uniformity that cannot be obtained through conventional laser methods.
2Manufacturing precision
If larger area enclosures are used for I/O bumps, then manufacturing errors are reduced, but package area increases
Solution Approach 1:
By replacing laser drilling with ICP etching, the patent achieves such high precision in I/O bump formation that smaller area enclosures can be used without increasing overlay shift. The plasma-based process provides superior control over etch depth and lateral dimensions, allowing compact packaging while maintaining manufacturing precision.
3Productivity
If smaller pitch I/O bumps are produced, then I/O density increases, but solder-I/O bump joint strength deteriorates
Solution Approach 1:
The patent uses ICP etching parameters to create optimized trench profiles with controlled depth and width, exposing precisely the right amount of underlying substrate and I/O bump. This parameter control ensures adequate solder wetting area even at smaller pitches, maintaining joint strength while increasing I/O density.
Solution Approach 2:
The etching process creates locally optimized features at each I/O bump location, with trench depths and profiles tailored to the specific bump dimensions. This local quality control ensures that each solder joint has optimal geometry for strength, regardless of the overall pitch size across the package.
4Ease of manufacture
If laser drill operations are used, then manufacturing cost is lower for simple processes, but costs increase due to manufacturing errors and rework
Solution Approach 1:
The patent replaces laser drilling with ICP etching, a process that inherently provides better precision and fewer manufacturing errors. Although the equipment is more complex, the reduction in rework, scrap, and yield loss results in lower overall manufacturing costs, especially for high-volume production where precision matters most.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of semiconductor packages with smaller pitch I/O bumps, reduced manufacturing errors, and lower costs by ensuring better critical dimension uniformity and solder-I/O bump joint strength, while eliminating the need for extensive laser drilling.
Implementation Method 1
a manufacturing method involving lithography and dry etching instead of laser drilling
Implementation Method 2
a seed layer is placed between the trench and the I/O bump
Data Source
AI summary
The present disclosure provides a semiconductor package, including a semiconductor die layer and a through insulator via (TIV). The semiconductor die layer has an active surface. The TIV is electrically coupled to the active surface. The TIV includes a body and a mesa. The body is surrounded by molding compound. The mesa has a tapered sidewall over the body. A portion of the tapered sidewall is covered by a seed layer.