TLB Access Filtering Against Translation Request Flooding

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Solution Overview

Problem

Existing network interface devices face performance degradation due to Denial of Service (DoS) attacks that cause excessive address translation requests, leading to increased latency and PCIe traffic bottlenecks by malicious processes evicting entries from the Translation Lookaside Buffer (TLB), affecting multiple hosts and virtual machines.

Innovation Solution

Implementing a TLB access filter to detect and mitigate DoS attacks by counting evictions and limiting access to the TLB indices for malicious processes, reducing their ability to evict entries and thereby controlling the number of address translation requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If address translation requests are permitted without restriction, then address translation functionality is maintained, but DoS attacks cause excessive PCIe traffic and performance degradation

Engineering Contradiction:
Improveaddress translation functionalityVSAvoidPCIe traffic volume
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

A TLB access filter is introduced as an intermediary component between the address translation requests and the TLB. This filter monitors eviction requests and determines whether to permit or block them based on security policies, thereby preventing malicious processes from causing excessive PCIe traffic while allowing legitimate address translation operations to proceed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback by monitoring TLB eviction requests and adjusting access permissions dynamically. When excessive evictions are detected from a particular process, the filter responds by blocking further eviction requests from that process, creating a closed-loop control mechanism that prevents DoS attacks without affecting legitimate operations

Inventive Principle:
Principle #23Feedback

2Speed

If TLB eviction is permitted freely, then address translation updates are efficient, but malicious processes can evict entries and increase latency

Engineering Contradiction:
Improveaddress translation update speedVSAvoidmemory access latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The TLB access filter acts as an intermediary that intercepts eviction requests before they reach the TLB. By filtering out malicious eviction requests while permitting legitimate ones, the filter maintains efficient address translation updates without allowing malicious processes to increase memory access latency through excessive evictions

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If unrestricted access to TLB is allowed, then address translation cache is fully utilized, but noisy neighbors can degrade performance of other PCIe functions

Engineering Contradiction:
ImproveTLB utilizationVSAvoidPCIe function performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The TLB access filter serves as a mediator that monitors and controls access to the TLB by different PCIe functions. It identifies noisy neighbor processes and blocks their eviction requests, thereby preventing them from degrading the performance of other PCIe functions while maintaining full TLB utilization for legitimate operations

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The filter applies different access policies to different processes or PCIe functions based on their behavior. Legitimate processes receive full access to the TLB, while identified malicious processes have their access restricted, creating localized quality control that protects overall system performance

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12596654B2Protection against translation lookup request flooding
Publication Date: 2026.04.07 INTEL CORP
  • US12596654B2 patent drawing
  • US12596654B2 patent drawing
  • US12596654B2 patent drawing

AI summary

Examples described herein relate to circuitry to permit evictions of entries from a Translation Lookaside Buffer (TLB) by one or more functions or hosts and limit evictions of entries from the TLB by one or more other functions or hosts. Limiting evictions of entries from the TLB by one or more other functions or hosts can be based on a number of TLB entry evictions from the TLB over an amount of time. Limiting evictions of entries from the TLB by one or more other functions or hosts can occur by reducing a number of indices available to the one or more functions or hosts.