TLB Reach via Instruction Cache Eviction
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Solution Overview
Problem
Current virtual address translation schemes in computer systems face inefficiencies due to high access latency and miss handling in translation lookaside buffers, leading to suboptimal performance in address translation management.
Innovation Solution
The proposed solution involves detecting misses in translation lookaside buffers and evicting address translations into instruction caches or local data shares, where they are stored and retrieved efficiently, optimizing the memory access hierarchy to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address translations are stored in translation lookaside buffer, then address translation speed is improved, but buffer capacity is limited causing misses
Solution Approach 1:
The patent implements a nested cache hierarchy where the translation lookaside buffer (TLB) is nested within the instruction cache structure. The TLB uses the same physical storage space as instruction cache entries, with the difference being how the data is interpreted and accessed. This nesting allows the TLB to leverage the existing cache infrastructure without requiring separate dedicated storage space, thereby resolving the contradiction between buffer capacity and translation speed.
Solution Approach 2:
The patent makes the instruction cache entries serve dual purposes: storing both instructions and address translations. By implementing multi-functionality in the cache structure, the system can use the same hardware resources for both instruction caching and translation buffering, effectively increasing the capacity available for address translations without adding separate buffer hardware.
2Productivity
If translation lookaside buffer is frequently evicting entries, then buffer reach is improved, but access latency increases
Solution Approach 1:
The patent implements preliminary action by pre-fetching address translations into the instruction cache/TLB structure before they are actually needed for memory access. The system proactively loads translations that are likely to be required soon, based on program execution patterns and address space usage, thereby reducing the latency when translations are finally needed while maintaining high buffer reach through continuous pre-loading.
3Adaptability or versatility
If instruction cache is used for address translations, then resource utilization is improved, but data collision occurs
Solution Approach 1:
The patent segments the cache structure into distinct functional zones: a dedicated translation lookaside buffer region and an instruction cache region. Within the TLB region, entries are further segmented by virtual address space or process context to prevent data collisions. This segmentation allows multiple data types to coexist in the same physical cache structure while maintaining logical separation and preventing interference between different cached data.
Data Source
AI summary
Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.