Address Translation Cache Coalesced Multi-Hit Detection
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Solution Overview
Problem
Existing address translation caches face inefficiencies in managing coalesced TLB entries, leading to potential performance impacts due to the need to check for non-coalesced address translation data during allocation, which can increase power consumption and delay new virtual address lookups.
Innovation Solution
The implementation of control circuitry that determines a coalesced multi-hit indication to differentiate between software-induced and hardware-induced multiple hits, allowing coalesced address translation data to be allocated without immediate checks for non-coalesced data, thus optimizing resource usage and reducing performance impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If coalesced TLB entries are created to improve address translation cache utilization, then cache resource efficiency is improved, but performance impact increases due to additional checks for non-coalesced data during allocation
Solution Approach 1:
The patent segments the multiple hit detection into two distinct categories: coalesced multi-hits (indicated by a new coalesced multi-hit indication bit) and non-coalesced multi-hits. This segmentation allows the system to handle coalesced entries differently from non-coalesced entries, enabling efficient cache resource utilization while maintaining lookup performance by avoiding unnecessary checks for coalesced data.
Solution Approach 2:
The patent sets the coalesced multi-hit indication bit in advance when coalesced address translation data is allocated to the TLB. This preliminary action eliminates the need for additional checks during subsequent lookup operations, as the indication is already available when multiple hits are detected, thereby preventing performance degradation.
2Measurement precision
If additional lookup checks are performed to verify non-coalesced address translation data, then data accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts the coalesced status information into a separate indication bit (coalesced multi-hit indication) that is independently tracked. This extraction eliminates the need to perform additional lookup checks to verify whether coalesced data is present, as the indication is already available. Consequently, power consumption is reduced while data accuracy is maintained through the dedicated indication mechanism.
3Speed
If coalesced address translation data is allocated without immediate checks, then allocation speed is improved, but reliability may worsen due to potential undetected non-coalesced data
Solution Approach 1:
The patent implements a feedback mechanism through the coalesced multi-hit indication bit, which provides immediate information about the presence of coalesced data. When multiple hits are detected, this feedback indication allows the system to quickly determine whether the multi-hit is due to coalesced or non-coalesced data, enabling fast allocation decisions while maintaining data consistency through accurate identification.
Data Source
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AI summary
An apparatus and method are provided for efficient utilisation of an address translation cache. The apparatus has an address translation cache with a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each entry identifies whether the address translation data stored therein is coalesced or non-coalesced address translation data, and also identifies a page size for a page within the memory system that is associated with that address translation data. Control circuitry is responsive to a virtual address, to perform a lookup operation within the address translation cache to produce, for each page size supported by the address translation cache, a hit indication to indicate whether a hit has been detected for an entry storing address translation data of the associated page size. The control circuitry is further arranged to determine, from at least each hit indication for a page size that is able to be associated with coalesced address translation data, a coalesced multi-hit indication which is set when a hit is detected for both an entry containing coalesced address translation data and for an entry containing non-coalesced address translation data. The control circuitry is then arranged, when the lookup operation has completed, to determine whether multiple hits have been detected, and in that instance to reference the coalesced multi-hit indication to determine whether multiple hits have resulted from both coalesced address translation data and non-coalesced address translation data in the address translation cache. This provides an efficient and precise mechanism for distinguishing between multiple hits caused by hardware coalescing and multiple hits caused by software induced issues.