TLB Combination Entry Design for Reducing Misses
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Solution Overview
Problem
The limited cache space in the translation lookaside buffer (TLB) leads to a high frequency of TLB misses, resulting in delays and reduced processing efficiency due to the limited number of page table entries that can be stored, which hampers the translation of virtual addresses to physical addresses.
Innovation Solution
The method involves using combination entries in the TLB that represent multiple virtual-to-physical page mappings, allowing for exponential increase in the number of entries, thereby reducing TLB misses and improving processing efficiency by predicting physical page numbers using bit vector fields and flag bits for address prediction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the TLB stores a limited number of page table entries due to cache space constraints, then the TLB structure remains simple and fast, but TLB miss frequency increases causing processing delays
Solution Approach 1:
The patent combines multiple virtual page number mappings into a single TLB entry using a bit vector field. Each bit in the bit vector represents whether a specific virtual page number is mapped to the associated physical frame number, allowing one TLB entry to represent multiple virtual-to-physical page mappings simultaneously. This merging approach increases the effective capacity of the TLB without increasing its physical size, thereby reducing TLB miss frequency and processing delays while maintaining the simple and fast TLB structure.
2Productivity
If one TLB entry represents multiple virtual-to-physical page mappings, then TLB miss probability decreases, but the complexity of entry structure increases
Solution Approach 1:
The TLB entry structure is designed to serve multiple functions simultaneously. The bit vector field acts as both a mapping indicator (showing which virtual page numbers are mapped to the physical frame number) and a compact storage mechanism. This multi-functional design allows the TLB to handle multiple virtual-to-physical page mappings within a single entry without proportionally increasing structural complexity, as the same fields serve multiple purposes: the virtual page number field identifies the base virtual page, the bit vector specifies which variant pages are mapped, and the physical frame number provides the target physical address.
3Reliability
If the TLB uses traditional one-entry-one-mapping structure, then the entry structure remains simple, but the number of TLB entries is limited causing high TLB miss rate
Solution Approach 1:
The patent merges multiple virtual page number mappings into a single TLB entry by introducing a bit vector field. Each bit in the bit vector corresponds to a specific virtual page number offset, indicating whether that page is mapped to the associated physical frame number. This allows one TLB entry to effectively represent N different virtual-to-physical mappings (where N is the number of bits in the bit vector), thereby increasing the effective number of mappable pages without increasing the actual number of TLB entries, thus improving the TLB hit rate while maintaining a limited TLB size.
Data Source
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AI summary
A method for accessing an entry in a translation lookaside buffer TLB and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The virtual huge page number is an identifier of N consecutive virtual pages. The bit vector field includes N bits, the N bits are in a one-to-one correspondence with the N consecutive virtual pages, and the N bits are used to identify a page table existence status of the N consecutive virtual pages, respectively. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.