Hardware TLB Conflict Resolution via Translation Preference Indicators
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Solution Overview
Problem
Processor-based systems face inefficiencies and memory faults due to translation lookaside buffer (TLB) conflicts during page table consolidation, which require software intervention and are exacerbated by modern architectural features like virtualization and multi-system MMUs.
Innovation Solution
Incorporating translation preference indicators in page table entries cached in the TLB, allowing the Memory Management Unit (MMU) to resolve conflicts by selecting TLB entries with set indicators over conflicting ones, thereby avoiding memory faults and reducing the need for software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If page table consolidation is performed to free memory, then memory utilization is improved, but TLB conflicts occur causing memory faults
Solution Approach 1:
The patent sets the translation preference indicator in the higher-level page table entry before invalidating the lower-level page table mappings. This preliminary action ensures that when TLB conflicts occur during consolidation, the hardware can immediately resolve them by preferring the higher-level entry, preventing memory faults while allowing consolidation to proceed
Solution Approach 2:
The translation preference indicator acts as an intermediary mechanism between conflicting TLB entries. It provides a hardware-based resolution method that mediates conflicts without requiring software intervention, allowing the system to maintain reliability during memory optimization operations
2Reliability
If break before make approach is used to prevent TLB conflicts, then memory fault occurrence is reduced, but system performance deteriorates due to temporary mapping breaks
Solution Approach 1:
Instead of breaking mappings before making new ones, the patent preliminarily sets the translation preference indicator in the higher-level entry while the old mappings are still valid. This allows continuous operation without temporary mapping breaks, maintaining system performance while preventing conflicts through hardware-based preference resolution
Solution Approach 2:
The MMU hardware automatically resolves TLB conflicts using the translation preference indicator without requiring software intervention or mapping breaks. This self-service mechanism eliminates the performance penalty associated with the break before make approach while maintaining reliability
3Reliability
If software intervention is used to handle TLB conflicts, then conflict resolution is achieved, but processing overhead increases
Solution Approach 1:
The patent implements hardware-based conflict resolution where the MMU automatically detects and resolves TLB conflicts using the translation preference indicator. This eliminates the need for software intervention, significantly reducing processing overhead and time loss while maintaining reliable conflict resolution
Solution Approach 2:
The patent replaces the software-based conflict resolution mechanism with a hardware-based mechanism using the translation preference indicator in the MMU. This substitution eliminates the overhead of software context switches and processing, providing faster and more efficient conflict resolution
Data Source
AI summary
Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems is disclosed. In this regard, in one aspect, a memory system provides a memory management unit (MMU) and multiple hierarchical page tables, each comprising multiple page table entries comprising corresponding translation preference indicators. The memory system further includes a TLB comprising multiple TLB entries each configured to cache a page table entry. The MMU determines whether a TLB conflict exists between a first TLB entry caching a first page table entry comprising a translation preference indicator that is set and a second TLB entry caching a second page table entry comprising a translation preference indicator that is not set. If so, the MMU selects the first TLB entry for use in a virtual-to-physical address translation operation, based on the translation preference indicator of the first page table entry cached by the first TLB entry being set.