TLB Consistency Directory for VIVT Cache Coherency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-performance processors face performance bottlenecks due to the need for extensive page table walks in virtual memory systems, which can be delayed by additional memory accesses, and existing TLB management instructions do not ensure hardware coherency with page tables, leading to potential stale translations.
Innovation Solution
A microprocessor with a virtually-indexed and virtually-tagged cache and a TLB consistency directory that uses hashed tags to efficiently invalidate cache entries in response to TLB management instructions, reducing the need for page table walks and maintaining coherency without requiring hardware-level consistency checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor includes hardware to maintain TLB consistency with page tables, then TLB coherency is improved, but device complexity increases
Solution Approach 1:
The patent introduces a TLB consistency directory as an intermediary data structure that stores hashed tags of page table entries. This directory acts as a mediator between the page tables and TLB, enabling efficient consistency checking without requiring complex hardware validation logic. The directory contains hash values that can be quickly compared against TLB entries to detect inconsistencies.
Solution Approach 2:
The patent replaces complex hardware-level consistency check mechanisms with a software-managed directory structure using hashed tags. Instead of implementing elaborate hardware circuits for TLB validation, the system uses a data structure (directory) that can be managed through standard processor operations, substituting mechanical/hardware complexity with a more manageable software-based approach.
2Measurement precision
If the processor performs full page table walks to verify TLB translations, then translation accuracy is improved, but processing time increases
Solution Approach 1:
The patent implements partial validation by comparing only hashed tags from the TLB consistency directory against TLB entries, rather than performing complete page table walks. This partial action (hash comparison) is sufficient to detect most inconsistencies without the full overhead of重新 traversing the entire page table hierarchy, thus maintaining translation accuracy while reducing processing time.
Solution Approach 2:
The TLB consistency directory is pre-populated with hashed tags from page table entries before TLB operations occur. This preliminary preparation allows for rapid consistency checking during TLB operations, as the hash values are already computed and stored, eliminating the need for time-consuming page table walks during critical translation operations.
3Speed
If the TLB caches more virtual address translations, then translation speed is improved, but the likelihood of stale translations increases
Solution Approach 1:
The patent implements a feedback mechanism where the TLB consistency directory continuously monitors page table changes and provides information back to the TLB management logic. When the directory detects that a cached TLB entry corresponds to a modified page table entry (through hash comparison), it triggers invalidation of the stale TLB entry, ensuring translation freshness while maintaining large cache capacity.
Solution Approach 2:
The TLB consistency directory serves as an intermediary monitoring layer between the page tables and the TLB cache. It observes changes in page table entries and mediates TLB invalidation decisions, allowing the TLB to maintain a large number of cached translations while relying on the directory to detect and eliminate stale entries through hash-based comparison.
Data Source
AI summary
A virtually-indexed and virtually-tagged cache has E entries each holding a memory line at a physical memory line address (PMLA), a tag of a virtual memory line address (VMLA), and permissions of a memory page that encompasses the PMLA. A directory having E corresponding entries is physically arranged as R rows by C columns=E. Each directory entry holds a directory tag comprising hashes of corresponding portions of a page address portion of the VMLA whose tag is held in the corresponding cache entry. In response to a translation lookaside buffer management instruction (TLBMI), the microprocessor generates a target tag comprising hashes of corresponding portions of a TLBMI-specified page address. For each directory row, the microprocessor: for each directory entry of the row, compares the target and directory tags to generate a match indictor used to invalidate the corresponding cache entry.