TLB Compression for Contiguous Virtual-to-Physical Mappings
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Solution Overview
Problem
Existing memory management techniques in computing systems are inefficient in terms of resource utilization and performance, particularly in handling large amounts of data, such as in machine learning processes, due to the limited capacity and efficiency of translation lookaside buffers (TLBs).
Innovation Solution
The proposed solution involves compressing multiple virtual and physical memory address mappings into a single entry in the TLB by leveraging contiguity and shared bits between addresses, allowing for a larger number of mappings without increasing storage size, through techniques that differentiate between VA and PA contiguity and shared attributes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple virtual and physical memory address mappings are compressed into a single TLB entry by leveraging contiguity and shared bits, then the number of mappings stored in the TLB increases, but the complexity of address translation and TLB entry structure increases
Solution Approach 1:
The patent segments the physical address into common bits (shared across multiple pages) and unique bits (specific to each page). The TLB entry stores the common bits once and uses segmentation to represent multiple virtual-to-physical mappings by combining the common bits with page offset information, thereby increasing the number of mappings stored while managing complexity through structured address decomposition.
Solution Approach 2:
The patent introduces a new dimension of address representation by storing not just direct virtual-to-physical mappings but also common address bits that can be combined with page offsets. This dimensional expansion allows a single TLB entry to represent multiple mappings by varying the page offset component, effectively increasing storage capacity without proportionally increasing entry count.
2Speed
If the TLB stores a smaller subset of translations to enable faster retrieval, then the search speed improves, but the capacity to store mappings decreases
Solution Approach 1:
The patent merges multiple virtual-to-physical mappings into a single TLB entry by identifying and storing common address bits that are shared across multiple physical pages. This consolidation reduces the total number of TLB entries needed while maintaining the ability to represent multiple mappings, thereby increasing effective capacity without sacrificing search speed.
Solution Approach 2:
The patent changes the parameter representation in TLB entries from storing complete physical addresses to storing common address bits combined with page offset information. This parameter transformation allows the same TLB entry size to represent multiple mappings, effectively increasing capacity while maintaining the compact structure needed for fast retrieval.
3Productivity
If contiguous physical memory addresses sharing common bits are identified and compressed, then resource utilization improves, but the complexity of determining contiguity and shared bits increases
Solution Approach 1:
The patent applies local quality by focusing on specific portions of the address structure (common bits versus page offset bits) rather than treating the entire address uniformly. By identifying contiguity in terms of shared common bits and systematically varying page offsets, the system improves resource utilization through compression while managing complexity through localized analysis of address segments.
Solution Approach 2:
The patent performs preliminary action by pre-identifying and storing common address bits before actual address translation occurs. This advance preparation allows the system to quickly determine contiguity and shared bits during operation, improving resource utilization while reducing the complexity of real-time determination through pre-computed common bit patterns.
Data Source
AI summary
Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.