TLB Maintenance Using Process-Specific Physical CPU Ranges
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current TLB consistency maintenance processes in multi-core systems are complex and result in significant delays, leading to decreased memory access performance.
Innovation Solution
Implement a method to determine and maintain a specific physical CPU range for each process or virtual machine, synchronously updating TLB information within this range using hardware, thereby reducing maintenance delays and overheads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TLB consistency maintenance is performed on all physical CPUs in a multi-core system, then TLB consistency is ensured, but maintenance delay and system overhead increase significantly
Solution Approach 1:
The patent segments the physical CPU range into a manageable subset based on process affinity. Instead of maintaining TLB consistency across all physical CPUs in the system, the invention identifies and maintains consistency only for the specific range of physical CPUs currently executing threads of the modifying process. This segmentation is achieved through process affinity tracking and physical CPU range determination, which narrows the scope of TLB shootdown operations to only affected CPUs, thereby reducing maintenance delay while ensuring consistency where needed.
2Reliability
If TLB consistency maintenance is performed on all physical CPUs, then TLB access errors are avoided, but memory access performance decreases
Solution Approach 1:
The patent applies local quality by tailoring the TLB consistency maintenance scope to the specific local context of process execution. Rather than applying uniform TLB shootdown across the entire system, the invention identifies the local physical CPU range where the modifying process is actually executing and maintains consistency only in that localized range. This is achieved through tracking which physical CPUs have active threads of the modifying process, thereby ensuring TLB correctness for affected areas while leaving other areas unaffected and operational.
3Reliability
If a broad TLB consistency maintenance approach is used, then TLB consistency is maintained, but system complexity increases
Solution Approach 1:
The patent implements self-service by leveraging existing process affinity tracking mechanisms and physical CPU range management that are already part of the operating system's process scheduling infrastructure. The invention reuses these existing self-service mechanisms to determine which physical CPUs should receive TLB shootdown notifications, avoiding the need for separate complex tracking systems. This approach allows the system to automatically identify affected CPUs based on process execution state without requiring additional complex management overhead.
Data Source
Figure 1
Figure 2~3
Figure 4a
AI summary
Embodiments of this application disclose a translation lookaside buffer maintenance method and a related device. The method is applied to an electronic device, the electronic device includes a plurality of physical central processing units CPUs, a first process is run on the electronic device, the first process currently includes M first threads, the M first threads are currently being respectively run on M physical CPUs of the plurality of physical CPUs, and M is an integer greater than or equal to 1. The method includes: determining a physical CPU range S1 currently corresponding to the first process, where the physical CPU range S1 includes the M physical CPUs on which the first threads in the first process are currently being run; and updating, based on page table information maintained by the first process, translation lookaside buffer TLB information maintained by all physical CPUs in the physical CPU range S 1. According to embodiments of this application, a TLB maintenance delay can be reduced.