TLB Translation Data Transfer for Task Migration Bottlenecks
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Solution Overview
Problem
In multiple processing element systems, task migration between processing elements leads to inefficiencies due to the need for repeated page table walks to populate translation lookaside buffers (TLBs) with relevant translation data, which is time-consuming and occurs when tasks are migrated or spawned, disrupting load balancing and thermal management.
Innovation Solution
Control circuitry is implemented to transfer a subset of translation data from one processing element's TLB to another, based on prediction or detection of task migration, using a migration tracking table and configuration data to identify relevant data and optimize transfer paths, ensuring seamless task execution across processing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If task migration between processing elements is allowed, then system adaptability and load balancing are improved, but translation data must be reloaded through page table walks which increases time consumption and reduces productivity
Solution Approach 1:
The patent transfers translation data from the source processing element's TLB to the destination processing element's TLB before the task migration is completed. This preliminary action ensures that when the task arrives at the destination, the translation data is already cached, eliminating the need for time-consuming page table walks and immediately reducing the time loss associated with task migration.
Solution Approach 2:
The patent introduces a control circuit as an intermediary component that manages the transfer of translation data between processing elements. This control circuit acts as a mediator that coordinates the TLB data transfer independently of the task migration process, allowing the translation data to be moved through an intermediate channel without blocking the main task execution path and thus reducing overall time consumption.
2Productivity
If translation data is transferred between processing elements, then task migration efficiency is improved, but device complexity increases due to additional control circuitry
Solution Approach 1:
The control circuit is designed to perform multiple functions: it manages TLB data transfer between processing elements, tracks the migration status of tasks, and coordinates with the memory management unit. By making the control circuit multi-functional, the patent reduces the need for separate dedicated components for each function, thereby improving task migration efficiency while minimizing the increase in device complexity.
Solution Approach 2:
The patent merges the translation data transfer function with the existing memory management infrastructure. The control circuit integrates with the memory management unit and utilizes existing TLB structures, combining multiple functions into unified components rather than adding entirely separate systems. This merging approach enhances task migration efficiency while keeping the overall device complexity manageable.
3Reliability
If page table walks are performed repeatedly for migrated tasks, then translation accuracy is maintained, but system performance deteriorates due to time-consuming operations
Solution Approach 1:
Instead of performing repeated page table walks to verify translation accuracy, the patent creates a copy of the translation data from the source processing element's TLB and places it in the destination processing element's TLB. This copying mechanism maintains translation accuracy by preserving the original translation data while eliminating the need for repeated verification walks, thus improving system performance without sacrificing reliability.
Solution Approach 2:
The patent performs the translation data transfer in advance before the migrated task needs to access memory at the destination processing element. By preliminarily populating the destination TLB with the required translation data, the system maintains translation accuracy that would otherwise require repeated page table walks, while simultaneously improving productivity by eliminating these time-consuming verification operations during task execution.
Data Source
AI summary
Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.