TLB Entry Selection Using Address Space Identifiers
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Solution Overview
Problem
The existing data processing systems face inefficiencies in converting virtual addresses to physical addresses due to the limited capacity of the translation lookaside buffer (TLB), which leads to increased time and power consumption when a virtual address is not stored, and the selection method for overwriting entries in the TLB does not consistently prioritize mappings that are unlikely to be used soon.
Innovation Solution
The proposed solution involves address translation circuitry that uses additional data associated with each mapping, such as address space identifiers and global identifiers, to determine which entries in the TLB should be overwritten, thereby prioritizing the retention of mappings likely to be needed again, and includes a method for selecting entries based on this data to minimize TLB misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TLB stores a complete mapping of virtual to physical addresses, then translation accuracy is improved, but the device complexity and power consumption increase significantly
Solution Approach 1:
The patent segments the complete virtual-to-physical address mapping into two parts: a complete mapping stored in main memory, and a subset of recently used mappings stored in the TLB. This segmentation allows the system to maintain high translation accuracy through the complete mapping while keeping the TLB simple and fast by storing only essential recent mappings.
Solution Approach 2:
The patent extracts the most frequently accessed virtual-to-physical address mappings from the complete mapping and places them in the TLB. This extraction strategy ensures that the TLB contains only the mappings that are most likely to be needed soon, improving translation speed while maintaining overall accuracy through the complete mapping in main memory.
2Productivity
If the TLB stores more entries, then the frequency of TLB misses is reduced, but the time to select which entry to overwrite increases
Solution Approach 1:
The patent applies preliminary action by pre-selecting candidate entries for overwriting based on additional data stored with each mapping entry. Before a TLB miss occurs, the system has already organized the entries with their associated additional data, enabling rapid identification of suitable candidates for overwriting when a miss occurs, thus reducing the time loss.
Solution Approach 2:
The patent uses feedback mechanisms by storing additional data with each TLB entry that provides information about the likelihood of future use. This feedback information guides the selection of entries to overwrite, allowing the system to make informed decisions quickly without examining all entries, thereby balancing TLB size benefits with minimal selection time.
3Ease of manufacture
If conventional selection methods (random, round robin, least recently accessed) are used to overwrite TLB entries, then the implementation is simple, but the performance deteriorates due to overwriting frequently used mappings
Solution Approach 1:
The patent introduces feedback by storing additional data with each TLB entry that provides information about the likelihood of future use. This feedback mechanism allows the system to identify entries that are unlikely to be needed soon and prioritize them for overwriting, thereby avoiding the performance deterioration caused by conventional methods that may overwrite frequently used mappings.
Solution Approach 2:
The patent changes the parameters used for entry selection by incorporating additional data associated with each mapping entry. Instead of relying solely on simple criteria like recency or position, the system uses the additional data parameter to make more informed selection decisions, improving data access performance while maintaining reasonable implementation complexity.
Data Source
AI summary
Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.