TLB Error Entry Storage for Speculative Page Fault Prevention
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Solution Overview
Problem
In data processing systems, repeated speculative execution of instructions causing translation faults leads to wasteful page walks, as each execution initiates a time-consuming page walk process to determine the corresponding physical address, even if the translation error is consistent, resulting in inefficient use of processing resources.
Innovation Solution
Implementing a data processing apparatus with lookup circuitry that speculatively executes instructions, performs page walks when virtual addresses are unlisted, and stores error entries in the Translation Lookaside Buffer (TLB) to prevent repeated page walks by signaling errors and storing virtual addresses, allowing direct access or marking entries as faulting to avoid unnecessary page walks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If speculative execution is used to execute instructions before branch resolution, then processing efficiency is improved, but repeated page walks are triggered for faulting translations
Solution Approach 1:
The patent stores the virtual address in the TLB storage circuitry when a translation fault is detected during speculative execution. This preliminary action ensures that subsequent speculative executions of the same instruction will find the address in the TLB and can properly handle the translation fault without initiating another page walk, thus resolving the contradiction by preparing the system in advance to avoid repeated time-consuming operations.
2Reliability
If page walks are performed for each speculative execution with translation faults, then correct translation can be determined, but processing resources are wasted
Solution Approach 1:
The patent implements a feedback mechanism where the result of a page walk (the determined correct translation or the detection of an invalid translation) is stored in the TLB storage circuitry. This feedback allows the system to learn from previous page walk results and avoid repeating them, thereby maintaining translation correctness while reducing processing resource waste by eliminating redundant page walks for the same virtual addresses.
Data Source
AI summary
There is provided a data processing apparatus comprising: processing circuitry to speculatively execute an instruction referencing a virtual address. Lookup circuitry receives the virtual address from the processing circuitry. The lookup circuitry comprises storage circuitry to store at least one virtual address and page walking circuitry to perform a page walk on further storage circuitry, in dependence on the virtual address being unlisted by the storage circuitry, to determine whether a correspondence between a physical address and the virtual address exists. The lookup circuitry signals an error when the correspondence cannot be found and, in response to the error being signaled, the storage circuitry stores an entry comprising the virtual address.