TLB Exception Handling for Timing Attack Prevention
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Solution Overview
Problem
Conventional Translation Lookaside Buffers (TLBs) are vulnerable to timing attacks due to differences in processing time between TLB hits and misses, which can expose privileged memory areas to software with lower privilege levels, compromising system security.
Innovation Solution
The proposed arithmetic processing device incorporates a dual-access management system, where the first access management unit determines access authorization for virtual addresses and outputs notifications for unsuitable requests, and the second access management unit translates addresses and notifies the control unit of access prohibitions, ensuring consistent response times for both hits and misses to prevent timing attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the TLB performs exception handling at high speed, then the address translation process is shortened and processing efficiency is improved, but the system becomes vulnerable to timing attacks that can expose privileged memory areas
Solution Approach 1:
The patent introduces an intermediary mechanism (the enhanced TLB exception handling system with extended validation) that mediates between the need for fast address translation and security requirements. By adding intermediate validation steps and统一的exception handling paths, the system maintains high speed while preventing timing attacks through consistent processing durations.
Solution Approach 2:
The patent changes the parameter of exception handling time to be consistent across different access scenarios. By modifying the exception handling process to always take the same amount of time regardless of whether it's a genuine exception or a timing attack probe, the system eliminates the timing vulnerability while maintaining productivity.
2Loss of time
If the TLB uses cached values for fast address translation, then processing time is reduced, but the system cannot distinguish between TLB hits and exception cases, creating security vulnerabilities
Solution Approach 1:
The patent segments the address translation process into distinct phases with clear validation points. By separating the cached value retrieval from the authorization validation and exception handling, the system can maintain fast processing for legitimate cases while ensuring security through structured validation segments that prevent confusion between hits and exceptions.
Solution Approach 2:
The patent performs preliminary validation of access authorization before completing the address translation process. By checking authorization credentials in advance and establishing a unified exception handling path, the system prepares for potential security issues before they arise, ensuring that both legitimate fast paths and exception cases are handled securely without timing vulnerabilities.
Data Source
AI summary
A TLB receives an access request with respect to a first address and access authorization assigned to the request from an arithmetic operation control unit, translates the first address to a second address, determines the suitability of the access authorization, and outputs the access request with respect to the first address when the access authorization is not suitable. An MMU receives the access request with respect to the first address output from the TLB, translates the first address to the second address, determines the suitability of the access authorization, and outputs a notification of access prohibition to the arithmetic operation control unit when the access authorization is not suitable.