TLB Entries With Exclusion Bits For Mixed Page Sizes

The patent divides a large page into multiple smaller subpages, allowing the TLB to represent a contiguous range of memory with a single entry rather than requiring multiple separate entries. This segmentation approach enables flexible mixing of page sizes while reducing TLB entry requirements by creating a hierarchical structure where large pages can contain smaller subpages.

The patent introduces an exclusion bit field that adds a new dimension to the TLB entry structure. This exclusion bit field allows the system to exclude specific subpage ranges from a large page, enabling precise control over which memory regions are covered by the TLB entry. This dimensional addition resolves the contradiction by providing both flexibility and entry reduction simultaneously.

The patent makes the page structure dynamic by allowing large pages to be divided into smaller subpages on demand. The exclusion bit field dynamically specifies which subpages are excluded from the large page coverage, enabling the system to adapt to different alignment requirements while maintaining the benefits of large page TLB entries. This dynamic structure resolves the rigidity of fixed alignment requirements.

The patent applies different page size qualities to different regions of memory by using exclusion bits to specify which subpages are excluded from large page coverage. This allows local optimization where specific memory regions can have different effective page sizes based on their alignment requirements, while the overall TLB entry remains efficient. Each region can have tailored page characteristics without affecting the entire TLB structure.

The patent merges multiple potential TLB entries into a single entry by using the exclusion bit field to represent a contiguous range of memory. Instead of requiring separate TLB entries for each page or subpage in a contiguous range, the system combines them into one entry that covers the entire range while excluding specific subpages as needed. This merging reduces system complexity while preserving memory continuity.

The patent changes the parameter structure of TLB entries by adding the exclusion bit field, which fundamentally alters how contiguous memory ranges are represented. This parameter change enables a single TLB entry to cover a contiguous range with selective exclusions, reducing the number of entries needed while maintaining continuity. The exclusion bits provide a compact way to specify which regions are included or excluded without increasing overall system complexity.