TLB Filter Directory for Selective Invalidation
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Solution Overview
Problem
Modern computing systems face performance issues due to unnecessary translation lookaside buffer invalidation instructions (TLBIs) being sent to processing elements, especially in multi-core systems, which can lead to adverse effects on system performance.
Innovation Solution
A method and apparatus that utilize a filter, known as a translation lookaside buffer directory cache, to determine which processing elements have specific mappings in their TLBs, allowing for selective invalidation of TLB entries by partitioning processing elements based on the presence of mappings, thereby suppressing unnecessary TLBI instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If translation lookaside buffer invalidation instructions are sent to all processing elements, then all TLB entries are invalidated, but system performance deteriorates due to unnecessary invalidations
Solution Approach 1:
The patent segments the set of processing elements into two partitions based on whether they have the specific mapping in their TLBs. The filter structure divides the invalidation distribution into selective groups, sending TLBI instructions only to partition one (elements with the mapping) and suppressing them for partition two (elements without the mapping), thus avoiding unnecessary invalidations while maintaining completeness where needed
Solution Approach 2:
The patent applies local quality by customizing the invalidation behavior for different processing elements based on their individual TLB state. Instead of uniform invalidation, the system determines locally whether each processing element has the specific mapping and tailors the invalidation instruction delivery accordingly, sending TLBI only to elements that actually have the mapping present
2Productivity
If a filter is introduced to track mapping presence, then unnecessary TLBIs are suppressed, but device complexity increases
Solution Approach 1:
The patent makes the filter structure multi-functional by having it serve multiple purposes: tracking which processing elements have specific mappings in their TLBs, partitioning elements based on mapping presence, and controlling TLBI instruction delivery. This universal filter structure handles multiple functions that would otherwise require separate mechanisms, justifying the added complexity through functional consolidation
Solution Approach 2:
The filter acts as an intermediary component between the invalidation instruction source and the processing elements. It mediates the invalidation process by first determining which elements have the mapping and then selectively distributing TLBI instructions accordingly, preventing unnecessary invalidations from reaching elements that don't have the mapping
Data Source
AI summary
A filter includes filter entries, each corresponding to a mapping between a virtual memory address and a physical memory address and including a presence indicator indicative which processing elements have the mapping present in their respective translation lookaside buffers (TLBs). A TLB invalidation (TLBI) instruction is received for a first mapping. If a first filter entry corresponding to the first mapping exists in the filter, the plurality of processing elements are partitioned into a first partition of zero or more processing elements that have the first mapping present in their TLBs and a second partition of zero or more processing elements that do not have the first mapping present in their TLBs based on the presence indicator of the first filter entry. The TLBI instruction is sent to the processing elements included in the first partition, and not those in the second partition.