TLB Flush Broadcast via Bus for Multi-Core Consistency
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Solution Overview
Problem
Existing processor systems face inefficiencies in TLB flush operations across multiple processor cores, requiring software interrupts and inter-core communication, which degrade performance due to the need for individual hardware threads to update their TLBs independently.
Innovation Solution
A new instruction processing apparatus and method that broadcasts TLB flush instructions on a bus, allowing other processing units to receive and perform TLB purging operations, thereby improving efficiency by enabling simultaneous updates across hardware threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated TLB flush instruction is used in existing processor systems, then the TLB cache entries can be updated to ensure consistency with the page table, but the processing efficiency deteriorates because each hardware thread must separately execute the flush instruction through software interrupts and inter-core communication
Solution Approach 1:
The flush instruction is segmented into two distinct parts: a first operand containing address information and a second operand containing address space identification information. This segmentation allows receiving processing units to efficiently filter and process only relevant TLB entries matching the specified address space, avoiding unnecessary flush operations across all hardware threads and thereby improving processing efficiency while maintaining consistency.
Solution Approach 2:
The patent introduces a bus as an intermediary communication channel between processing units. When a processing unit executes the flush instruction, it broadcasts the address information and address space identification information via the bus to other processing units. This intermediary mechanism enables efficient multi-core communication without requiring complex inter-core interrupt handling, allowing simultaneous TLB flush operations across multiple hardware threads.
2Reliability
If software interrupts and inter-core interrupt communication mechanisms are used to notify other hardware threads of page table changes, then TLB consistency can be maintained across cores, but the system complexity increases due to the need for interrupt handling and separate execution coordination
Solution Approach 1:
The bus serves as a simplified intermediary that replaces complex inter-core interrupt communication mechanisms. Instead of using software interrupts and interrupt handlers, the executing processing unit directly broadcasts flush parameters (address information and address space identification) through the bus to other processing units. This approach significantly reduces system complexity by eliminating the need for interrupt coordination while maintaining cross-core TLB consistency.
Solution Approach 2:
Other processing units autonomously monitor the bus for flush instructions and independently execute TLB flush operations based on the broadcast address information and address space identification. This self-service mechanism eliminates the need for centralized interrupt coordination and separate execution coordination, allowing each processing unit to handle its own TLB maintenance independently while ensuring cross-core consistency.
Data Source
AI summary
The present invention discloses an instruction processing apparatus, including: a first register adapted to store address information; a second register adapted to store address space identification information; a decoder adapted to receive and decode a translation lookaside buffer flush instruction, where the translation lookaside buffer flush instruction indicates that the first register serves as a first operand, and the second register serves as a second operand; and an execution unit coupled to the first register, the second register, and the decoder and executing the decoded translation lookaside buffer flush instruction, so as to acquire address information from the first register, to acquire address space identification information from the second register, and to broadcast the acquired address, information and address space identification information on a bus coupled to the instruction processing apparatus, so that another processing unit coupled to the bus performs purging on a translation lookaside buffer, corresponding to the address information, in an address space indicated by the address space identification information. The present invention also discloses a corresponding instruction processing method, a computing system, and a system-on-chip.