TLB Hint Data for Heterogeneous Memory Power Management

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current data processing systems face inefficiencies in managing memory access across heterogeneous memory systems, as they lack effective mechanisms to optimize storage based on the access patterns and performance characteristics of different memory types, leading to suboptimal power consumption and latency.

Innovation Solution

The system employs mapping circuitry to store virtual-to-physical address mappings and hint generating circuitry to control storage based on the storage of these mappings, allowing for dynamic power management and type selection of memory banks according to access patterns, thereby optimizing storage across different memory types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If all memory banks are kept active to ensure fast access, then access latency is reduced, but power consumption increases

Engineering Contradiction:
Improvememory access speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the memory system configuration changeable based on access patterns. The system dynamically adjusts which memory banks are active or inactive, and which memory types are used for different data regions, based on real-time or near-real-time analysis of access patterns. This allows the system to optimize between speed and power consumption by adapting the memory architecture to actual usage requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes key parameters of the memory system including memory bank activation status, memory type allocation, and access policies based on analyzed access patterns. By monitoring which memory regions are accessed frequently and which are rarely accessed, the system changes parameters such as powering down inactive banks or relocating data to optimize the balance between performance and energy consumption.

Inventive Principle:
Principle #35Parameter changes

2Speed

If mapping data entries are stored in TLB to enable fast virtual-to-physical address translation, then translation speed is improved, but memory space consumption increases

Engineering Contradiction:
Improveaddress translation speedVSAvoidmemory space
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies local quality by differentiating the treatment of different memory regions based on their access characteristics. Instead of uniformly managing all memory the same way, the system identifies locally optimal strategies for different regions - for example, keeping frequently accessed regions in fast memory while allowing less frequently accessed regions to use slower memory or be evicted from TLB. This localized optimization allows efficient use of limited TLB space.

Inventive Principle:
Principle #3Local quality

3Use of energy by moving object

If heterogeneous memory types are used to optimize performance and power, then energy efficiency is improved, but system complexity increases

Engineering Contradiction:
Improveenergy efficiencyVSAvoidmemory system complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies self-service by implementing an automated memory management system that independently analyzes access patterns and makes intelligent decisions about memory allocation and power management. The system includes self-contained components for monitoring, analyzing, and controlling memory resources without requiring external intervention. This automated approach manages the complexity internally while presenting a simplified interface to the rest of the system.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10162762B2Managing memory based on hint data generated from mapping data entries
Publication Date: 2018.12.25 ARM LTD
  • US10162762B2 patent drawing
  • US10162762B2 patent drawing
  • US10162762B2 patent drawing

AI summary

A data processing system 4 includes a translation lookaside buffer 6 storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the translation lookaside buffer 6 generates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer 6. The hint generator 20 tracks the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer 6. The hint data is supplied to a memory controller 8 which controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions.