Multithreaded TLB Invalidation via Non-Blocking Channels
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Solution Overview
Problem
In multithreaded data processing systems, the strict serialization of TLB invalidate entry instructions and associated synchronization instructions leads to performance penalties and potential deadlocks due to stalls in shared facilities, causing high latency and coherence issues across processor cores.
Innovation Solution
A method where storage-modifying and synchronization requests, including translation invalidation requests, are received in a shared queue and iteratively broadcast through sidecar logic until all processor cores complete processing, using a non-blocking channel for translation invalidation requests to ensure coherence without deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TLB invalidate entry instructions and synchronization instructions are strictly serialized, then coherence consistency across processor cores is maintained, but performance deteriorates due to large penalties and potential deadlocks
Solution Approach 1:
The patent segments the TLB invalidation process into two distinct phases: a broadcast phase where invalidation requests are sent to all processor cores, and a completion phase where synchronization is verified. This segmentation allows concurrent processing of invalidation requests while maintaining coherence consistency, eliminating the need for strict serialization and reducing performance penalties.
Solution Approach 2:
The patent implements preliminary action by broadcasting TLB invalidation requests to all processor cores before completing the invalidation process. The initiating processor core sends invalidation requests to all cores, including itself, and then waits for completion signals. This preliminary broadcast ensures that all cores are aware of the invalidation before the process completes, maintaining coherence without requiring strict instruction serialization.
2Reliability
If TLB invalidate entry instructions are strictly serialized, then coherence consistency is maintained, but latency increases due to stalls in shared facilities
Solution Approach 1:
The patent introduces dynamic behavior to the TLB invalidation process by allowing the initiating processor core to continue executing instructions while other cores process invalidation requests concurrently. The core dynamically transitions from a blocking serialized state to a non-blocking concurrent state, reducing latency while maintaining coherence consistency through proper synchronization mechanisms.
Solution Approach 2:
The patent ensures continuity of useful action by allowing the initiating processor core to execute subsequent instructions without waiting for the complete invalidation process to finish. The core sends invalidation requests, then continues executing other instructions while monitoring for completion signals, thereby eliminating stalls and reducing latency while maintaining coherence.
3Reliability
If multiple TLB invalidate entry instructions are executed in a hardware thread, then translation coherence is maintained, but performance deteriorates due to cumulative serialization penalties
Solution Approach 1:
The patent segments the execution of multiple TLB invalidation instructions by allowing them to be processed concurrently across different hardware threads. Each thread can send its invalidation requests independently, and the system coordinates completion through synchronization signals, eliminating cumulative serialization penalties while maintaining translation coherence.
Solution Approach 2:
The patent implements preliminary action by having each hardware thread send its TLB invalidation requests immediately upon execution, without waiting for previous requests to complete. The system then coordinates the completion of all requests through synchronization signals, allowing multiple invalidations to proceed concurrently and eliminating cumulative performance penalties.
Data Source
AI summary
In a multithreaded data processing system including a plurality of processor cores and a system fabric, translation entries can be invalidated without deadlock. A processing unit forwards translation invalidation request(s) received on the system fabric to a processor core via a non-blocking channel. Each of the translation invalidation requests specifies a respective target address and requests invalidation of any translation entry in the processor core that translates its respective target address. Responsive to a translation snoop machine of the processing unit snooping broadcast of a synchronization request on the system fabric of the data processing system, the translation synchronization request is presented to the processor core, and the translation snoop machine remains in an active state until a signal confirming completion of processing of the one or more translation invalidation requests and the synchronization request at the processor core is received and thereafter returns to an inactive state.