TLB Invalidation via Segmented Stage-1 and Stage-2 Commands
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Solution Overview
Problem
Current data processing systems with two-stage address translation face inefficiencies in TLB invalidation, particularly when dealing with combined stage-1-and-2 entries, leading to over-invalidation and performance issues in worst-case scenarios, especially for devices requiring real-time performance like display controllers.
Innovation Solution
The introduction of two types of TLB invalidation instructions: one targeting intermediate addresses and another with context-based conditions, allowing for precise invalidation of affected entries without over-invalidating unrelated data, and the use of tracking structures to optimize invalidation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single type of TLB invalidation command is used to handle both stage 1 and stage 2 translations, then the invalidation process is simplified, but it causes over-invalidation of unrelated entries and performance degradation in worst-case scenarios
Solution Approach 1:
The patent segments the TLB invalidation process into two distinct command types: first type commands for stage 2 intermediate address invalidation and second type commands for stage 1 virtual address invalidation. This segmentation allows each command type to target specific translation stages, preventing over-invalidation of unrelated entries while maintaining manageable command structures.
Solution Approach 2:
The patent applies local quality by making different TLB components (stage 1 TLB and stage 2 TLB) have different response characteristics to invalidation commands. The stage 2 TLB responds to first type commands with intermediate address matching, while the stage 1 TLB responds to second type commands with virtual address matching, optimizing each component's behavior for its specific function.
2Speed
If the TLB stores combined stage-1-and-2 entries to improve translation speed, then address translation performance is improved, but it becomes difficult to invalidate specific entries without over-invalidating
Solution Approach 1:
The patent implements dynamic behavior in combined TLB entries by introducing a stage field that can take different values. When the stage field indicates stage 2, the entry responds to first type invalidation commands with intermediate address matching. When the stage field indicates stage 1, the entry responds to second type invalidation commands. This dynamic characteristic allows combined entries to maintain fast translation while enabling precise invalidation based on the current operation mode.
Solution Approach 2:
The patent uses partial action by implementing optional second field information in combined TLB entries that indicates whether the entry should be invalidated by first type or second type commands. This partial information allows the system to achieve precise invalidation when needed while maintaining the performance benefits of combined entries, applying the level of precision appropriate to each specific case.
Data Source
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AI summary
A type of translation lookaside buffer (TLB) invalidation instruction is described which specifically targets a first type of TLB which stores combined stage-1-and-2 entries which depend on both stage 1 translation data and the stage 2 translation data, and which is configured to ignore a TLB invalidation command which invalidates based on a first set of one or more invalidation conditions including an address-based invalidation condition depending on matching of intermediate address. A second type of TLB other than the first type ignores the invalidation command triggered by the first type of TLB invalidation instruction. This approach helps to limit the performance impact of stage 2 invalidations in systems supporting a combined stage-1-and-2 TLB which cannot invalidate by intermediate address.