TLB Invalidation Suppression via Context Indicators

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Solution Overview

Problem

In computing systems with multiple processing elements, the broadcast of translation lookaside buffer (TLB) invalidate instructions leads to excessive bandwidth consumption and significant time penalties due to the large number of instructions and acknowledgments sent over the processing bus.

Innovation Solution

The method involves issuing instructions to invalidate entire contexts in translation lookaside buffers instead of individual entries, and suppressing subsequent TLB invalidate instructions for contexts that have already been invalidated, using a context indicator to manage these operations efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If individual TLB invalidate instructions are broadcast to all processing elements, then TLB consistency is maintained, but bandwidth consumption and time penalties increase significantly

Engineering Contradiction:
ImproveTLB consistencyVSAvoidbandwidth consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent combines multiple individual TLB invalidate instructions into a single context invalidate instruction. When a context switch occurs, instead of broadcasting separate invalidation messages for each TLB entry that needs invalidation, the system broadcasts a single instruction that invalidates all TLB entries associated with the outgoing context at all processing elements, thereby reducing bandwidth consumption while maintaining consistency

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary grouping of TLB entries by context identifier before invalidation. By organizing TLB entries according to their context associations in advance, the system can efficiently determine which entire context needs invalidation and broadcast a single preliminary invalidation instruction covering all relevant entries across all processing elements

Inventive Principle:
Principle #10Preliminary action

2Reliability

If individual TLB invalidate instructions are broadcast to all processing elements, then TLB consistency is maintained, but the time spent waiting for instruction completion increases

Engineering Contradiction:
ImproveTLB consistencyVSAvoidinstruction completion time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges multiple sequential invalidation operations into a single context-level invalidation operation. By combining what would otherwise be multiple separate broadcast instructions (each requiring acknowledgment and completion time) into one consolidated context invalidate instruction, the system reduces the total time spent waiting for instruction completion across all processing elements

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary identification of the context identifier that needs invalidation before broadcasting. This preliminary action allows the system to prepare a single comprehensive invalidation instruction that covers all necessary TLB entries across all processing elements, avoiding the need to sequentially send multiple individual invalidation instructions and wait for each to complete

Inventive Principle:
Principle #10Preliminary action

3Loss of energy

If context indicator is used to suppress redundant invalidation instructions, then bandwidth consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvebandwidth consumptionVSAvoidcontext indicator management
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism using context indicators stored at each processing element. Before broadcasting a context invalidate instruction, each processing element checks its local context indicator to determine whether the outgoing context identifier matches an already-invalidated context. This feedback loop prevents redundant invalidation broadcasts and reduces bandwidth consumption, while the indicator management overhead remains relatively simple

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9684606B2Translation lookaside buffer invalidation suppression
Publication Date: 2017.06.20 MARVELL ASIA PTE LTD
  • US9684606B2 patent drawing
  • US9684606B2 patent drawing
  • US9684606B2 patent drawing

AI summary

Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not: sending a corresponding instruction to the second processing element, causing invalidation of all TLB entries associated with the first context in the second TLB, and changing a state of the indicator; and if so: suppressing sending of any corresponding instructions for causing invalidation of any TLB entries associated with the first context in the second TLB to the second processing element.