Per-Process Memory Encryption via TLB Key Identifier Mapping
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Solution Overview
Problem
Current cryptographic virtual machine (VM) isolation architectures using multi-key total memory encryption (MKTME) face scalability issues due to the reduction in addressable memory size caused by encoding key identifiers in the system address space, which limits the number of keys that can be effectively used, especially with increasing core counts and emerging usage scenarios like FaaS.
Innovation Solution
Moving the encryption perimeter within each core of a multi-core processor, allowing each core to have its own encryption engine for per-process encryption and decryption, and using a system-specific wrapping key to manage keys, enabling seamless scaling to thousands of keys and fine-grain isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If key identifiers are encoded in the system address space to identify keys, then key identification is enabled, but addressable memory size is reduced
Solution Approach 1:
The patent introduces a new dimension for key identification by adding key identifier fields to page table entries and translation lookaside buffer (TLB) entries, rather than encoding keys directly in the address space. This allows the address space to remain intact while enabling multiple keys through extended metadata structures.
Solution Approach 2:
The patent embeds key identifier information within existing memory management structures (page tables and TLB), nesting the key identification capability inside these structures without requiring separate address space allocation. This allows key management to be integrated into the memory hierarchy without reducing addressable memory.
2Adaptability or versatility
If the number of keys is increased to support more VMs and processes, then cryptographic isolation is improved, but system complexity increases
Solution Approach 1:
The patent creates a universal key management system where page tables and TLB entries serve dual purposes: memory management and key identification. The same structures that manage virtual-to-physical address mapping also store key identifiers, eliminating the need for separate key management hardware or data structures.
Solution Approach 2:
The system enables key management to be handled automatically by the existing memory management unit (MMU) through software-configurable key fields in page tables and TLB entries. The MMU itself performs key identification without requiring additional dedicated key management logic, allowing the system to manage thousands of keys through existing infrastructure.
3Reliability
If encryption is performed at the memory controller level, then security is maintained, but key management overhead increases with scaling
Solution Approach 1:
The patent segments key management by allowing each core or processing unit to have its own key context associated with page tables and TLB entries. This segmentation enables independent key management for different cores or processes, reducing the overhead of centralized key management while maintaining security through localized encryption/decryption operations.
Data Source
AI summary
Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.