Contiguity-Aware TLB Mapping During Page Migration

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Solution Overview

Problem

Existing operating systems fail to maintain contiguity of virtual to physical address mappings during memory management activities such as page migration and reclamation, leading to inefficiencies in contiguity-aware translation look-aside buffers (TLBs) due to discontinuities introduced by NUMA balancing, hot/cold page promotion/demotion, memory compaction, and page reclamation.

Innovation Solution

Implement proactive strategies to maintain contiguity by adjusting page migration and reclamation processes, considering page attributes and virtual memory area attributes to minimize discontinuities, using an aggressive or defensive mode based on system conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional TLBs are used to map virtual to physical addresses, then each page can be mapped independently, but the number of TLB entries required becomes prohibitively large for large memory systems

Engineering Contradiction:

Improvenumber of TLB entriesVSAvoidaddress translation efficiency

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent merges multiple individual TLB entries into a single contiguity-aware TLB entry that can map N contiguous pages simultaneously. This consolidation reduces the total number of entries needed from millions (for traditional per-page mapping) to a manageable number, directly resolving the contradiction between entry quantity and translation efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The contiguity-aware TLB entry serves multiple functions by mapping N different virtual pages to N different physical pages within a single entry structure. This multi-functionality allows one TLB entry to replace what would traditionally require N separate entries, improving productivity while reducing quantity requirements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If page migration and reclamation operations are performed to manage memory, then memory pressure is reduced, but contiguity of address mappings is broken causing TLB inefficiency

Engineering Contradiction:

Improvememory management efficiencyVSAvoidmapping contiguity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary actions during page migration and reclamation operations to preserve contiguity. By proactively adjusting migration targets and reclamation selections based on contiguity constraints, the system prevents mapping discontinuities before they occur, maintaining TLB effectiveness while still achieving memory management goals.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameters of page migration and reclamation operations to respect contiguity constraints. By modifying migration decisions and reclamation criteria to consider mapping continuity, the system maintains the reliability of contiguity-aware TLBs while preserving memory management productivity.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If NUMA balancing is performed to optimize memory access, then performance is improved, but discontinuities are introduced in virtual to physical address mappings

Engineering Contradiction:

Improvememory access performanceVSAvoidmapping contiguity

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by considering different NUMA node characteristics and local memory access patterns when making migration decisions. By tailoring migration strategies to local conditions while preserving contiguity, the system achieves optimized performance without introducing harmful discontinuities to the address mapping structure.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12475059B2Maintaining contiguity of virtual to physical address mappings to exploit contiguity-aware translation look-aside buffer hardware

Publication Date: 2025.11.18 INTEL CORP

AI summary

Embodiments described herein are generally directed to maintaining contiguity of virtual to physical address mappings to exploit a contiguity-aware TLB. In an example, information regarding a migration set of one or more pages within a physical address space that have been identified for migration from a source tier of memory to a target tier of memory is received in which the physical address space comprises a first contiguous region of physical memory addresses and a VMA includes a second contiguous region of virtual memory addresses corresponding to the first contiguous region. It is determined whether the migration would break contiguity of a mapping maintained by a contiguity-aware TLB between pages of the first contiguous region and pages of the second contiguous region. Responsive an affirmative determination, discontinuities within the mapping resulting from the migration are minimized by intelligently increasing or decreasing the migration set.