Multi-Set TLB Lookup for Variable Page Sizes

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Solution Overview

Problem

Existing translation lookaside buffers (TLBs) face inefficiencies in handling multiple memory ranges due to the need for expensive fully associative structures and the complexity of managing different translation sizes, leading to increased lookup times and reduced performance.

Innovation Solution

The proposed solution involves a TLB design with an indexed memory array and size register array that allows for parallel indexing and comparison of candidate page sizes, enabling efficient translation of virtual memory addresses to physical addresses by determining possible indices and selecting matching page sizes, thereby reducing the number of lookups required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fully associative structure is used in TLB, then translation accuracy is improved, but device complexity and cost increase

Engineering Contradiction:
Improvetranslation accuracyVSAvoidstructure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the TLB into multiple sets (e.g., 4 sets), where each set contains a portion of the translation entries. This segmentation allows the system to perform parallel lookups across multiple sets simultaneously, maintaining high translation accuracy while reducing the complexity of any single set compared to a fully associative structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a set index dimension to organize TLB entries. Instead of a single fully associative structure, the TLB is organized as a multi-set associative structure where entries are distributed across sets indexed by certain bits of the virtual address. This dimensional organization enables parallel processing while controlling complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple translation sizes are supported, then adaptability is improved, but lookup time increases

Engineering Contradiction:
Improvetranslation size supportVSAvoidlookup time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent pre-calculates and stores the set index for each supported translation size (4KB, 64KB, 2MB, etc.). When a translation request arrives, the system immediately knows which set to search based on the pre-determined set index, eliminating the need for sequential searching across all sizes and significantly reducing lookup time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The TLB structure is designed to universally handle multiple translation sizes (4KB, 64KB, 2MB, and larger) within a single unified framework. The same multi-set associative structure and lookup mechanism work for all translation sizes, providing adaptability without requiring separate handling logic for each size.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If n lookups are performed for n different translation sizes, then translation completeness is improved, but productivity decreases

Engineering Contradiction:
Improvetranslation completenessVSAvoidlookup efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system pre-determines the set index for each translation size before the actual lookup occurs. This preliminary calculation allows the system to directly access the appropriate set without performing sequential lookups across all n translation sizes, maintaining translation completeness while dramatically improving lookup efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

By introducing the set index dimension and distributing entries across multiple sets, the system transforms the lookup process from a sequential search through n different translation sizes into a parallel lookup across multiple sets simultaneously, thereby improving productivity while ensuring translation completeness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10489303B2Multi-range lookup in translation lookaside buffer
Publication Date: 2019.11.26 ARM LTD
  • US10489303B2 patent drawing
  • US10489303B2 patent drawing
  • US10489303B2 patent drawing

AI summary

There is described a method and data processing apparatus configured to translate a virtual address into a physical address, the virtual address comprising an offset for a memory page, an index and a tag with the memory page having a variable size.