TLB Prefetch via Dummy Read Requests for Bus Masters
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Solution Overview
Problem
The latency associated with page table walks in virtual memory address translation can violate bandwidth and maximum latency requirements, particularly in applications with isochronous data flow such as video and audio, due to the inefficiency of translation lookaside buffer (TLB) misses.
Innovation Solution
A bus master circuit issues a dummy read request for the next virtual address page immediately after a read request, populating the TLB with the corresponding physical address mapping before data from the previous page is returned, thereby reducing page walk latency and ensuring the TLB is updated by the time the next page is accessed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If virtual memory address translation is performed using a translation lookaside buffer (TLB), then address translation speed is improved, but TLB misses cause page table walks that violate bandwidth and latency requirements
Solution Approach 1:
The bus master circuit issues a dummy read request for the next sequential page before the current page data is returned, pre-populating the TLB with the next page's physical address mapping. This preliminary action ensures that when the next page is accessed, its translation is already cached in the TLB, avoiding page table walks and reducing latency.
2Reliability
If the bus master waits for data from the current page before issuing the next read request, then data integrity is maintained, but sequential access efficiency is reduced
Solution Approach 1:
The system performs preliminary actions by issuing the dummy read request for the next page in advance, before the current page data transfer completes. This allows the TLB to be pre-populated without waiting for data integrity confirmation, and the dummy request is discarded after serving its prefetching purpose.
Solution Approach 2:
The dummy read request acts as an intermediary mechanism that bridges the gap between maintaining data integrity protocols and achieving sequential access efficiency. It triggers the TLB population without requiring the bus master to wait for data completion, thus mediating between reliability and productivity requirements.
Data Source
AI summary
Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.